read/write a file using memory core

I am trying to read/ write a file from mem.
here is my code. I have an error "" if any1 can help me.


ERROR:HDLCompilers:247 - "wr_file.v" line 34 Reference to vector wire 'data_out' is not a legal reg or variable lvalue
ERROR:HDLCompilers:106 - "wr_file.v" line 34 Illegal left hand side of nonblocking assignment


module wr_file(clk, we, add, data_in, data_out);
input clk, we;
input [3:0] add;
input [31:0] data_in;
output [31:0]data_out;
reg [31:0] memory[7:0];
always @(posedge clk)
begin
if(we)
memory[add] <= data_in;
else
data_out <= memory[add];
end

memory mem (
.clka(clk),
.wea(we), // Bus [0 : 0]
.addra(add), // Bus [2 : 0]
.dina(data_in), // Bus [31 : 0]
.douta(data_out));

endmodule

data_out <= memory[add];

Click to expand...

data_out is not a register so you cannot use the above statement. However, you already have instantiated a memory core and are driving data-out with it. You cannot drive data_out in two places.

The quoted statement, and in fact the whole always block, are made useless by the presence of the memory core. Get rid of one or the other.

r.b.

From my understanding this is a code for memory. I think you can use any one of the code below.


or


The first one the "reg memory" is act as memory. The second one the "module memory" is act as memory.

I am using 2nd code. but i m having warnings in it. and when i simulate it. i m not geting anything at output.

WARNING:Xst:2211 - "ipcore_dir/memory.v" line 38: Instantiating black box module <memory>.
WARNING:Xst:1780 - Signal <memory> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Here is my memor black box. i dnt know wat to do with this block. If yu plzz tell me


`timescale 1ns/1ps

module memory(
clka,
wea,
addra,
dina,
douta);


input clka;
input [0 : 0] wea;
input [2 : 0] addra;
input [31 : 0] dina;
output [31 : 0] douta;

// synthesis translate_off

BLK_MEM_GEN_V4_1 #(
.C_ADDRA_WIDTH(3),
.C_ADDRB_WIDTH(3),
.C_ALGORITHM(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("spartan3"),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_INPUT_REGS_B(0),
.C_HAS_SOFTECC_OUTPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(0),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(8),
.C_READ_DEPTH_B(8),
.C_READ_WIDTH_A(32),
.C_READ_WIDTH_B(32),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(8),
.C_WRITE_DEPTH_B(8),
.C_WRITE_MODE_A("NO_CHANGE"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(32),
.C_WRITE_WIDTH_B(32),
.C_XDEVICEFAMILY("spartan3"))
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC());


// synthesis translate_on

endmodule

I think the above code is generated from Xilinx Coregen, so if you are using this memory for simulation, then you must map the XilinxCoreLib library to the simulator.
The BLK_MEM_GEN_V4_1 should be there in the XilinxCoreLib.
The 2nd warning is because you are not commented thereg [31:0] memory[7:0];. I think so.