Dar89
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Hello,
I'm designing a circuit with a MSV approach. I have two power domain and one power mode, since i'm using a pure MSV approach.
I usually perform a gate level simulation on the synthesized netlist in order to extract the switching activities, which i export in tcf format. Therefore in rtl compiler i read the tcf and then have a report power.
My issue is born updating the rtl compiler version to 12.2. Indeed now, in MSV designs, if i read the tcf and the male a report power, the values appear very strange ( i'm synthesizing the circuit at 3ns, but the simulation to extract tcf is performed at 1us and i want the dinamic power at 1us for comparison purposes) being 3 orders of magnitude higher than expected. Moreover if i make a report power -power_mode the tool forgets the tcf data, using the default toggle rate. These issues didn't appear with the previous rtl compiler version. Moreover if i make a standard design, without MSV approach, all works fine.
Has anyone experience with this kind of issue ?
I'm designing a circuit with a MSV approach. I have two power domain and one power mode, since i'm using a pure MSV approach.
I usually perform a gate level simulation on the synthesized netlist in order to extract the switching activities, which i export in tcf format. Therefore in rtl compiler i read the tcf and then have a report power.
My issue is born updating the rtl compiler version to 12.2. Indeed now, in MSV designs, if i read the tcf and the male a report power, the values appear very strange ( i'm synthesizing the circuit at 3ns, but the simulation to extract tcf is performed at 1us and i want the dinamic power at 1us for comparison purposes) being 3 orders of magnitude higher than expected. Moreover if i make a report power -power_mode the tool forgets the tcf data, using the default toggle rate. These issues didn't appear with the previous rtl compiler version. Moreover if i make a standard design, without MSV approach, all works fine.
Has anyone experience with this kind of issue ?