Read enable Signal In SRAM array

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In SRAM array, to read the stored data in bit cell, 1 read enable signal is used . can any one please tell that, at cicuit level where the read enable signal is given in SRAM.
 

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How can anyone tell if you do not show your "cicuit level" SRAM?
Schematic, block diagram, anything MEANINGFUL which has the necessary info to answer your question!
 
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dpaul said:
How can anyone tell if you do not show your "circuit level" SRAM?
Schematic, block diagram, anything MEANINGFUL which has the necessary info to answer your question!
Click to expand...
if i have a circuit, why do i ask for it and those who know the operation of sram, they dont require anything MEANINGFUL. one can answer without diagram also
 

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no mention of 6T or 8T. no mention of how the decoder is implemented. no mention if the SRAM has a latched outputs. but OP insists one can answer without diagram! yikes.
 
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