read an image in vhdl

hi
my project is segmentation of carotid artery. Now i want to implement in fpga. For that i have to write code using vhdl. I simulate the code which you
posted earlier. IN THAT I GOT ONE ERROR(cannot continue because of fatal error)... please help with this....

What code?
What error?

Without posting this, or linking to them, we cannot help. So post the code, and copy and paste the error.

I tried with this code......


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use std.textio.all;


---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity image_read is

--port(
--type img_array_t is array(natural range <>, natural range <>) of natural;
--signal img_array : img_array_t(0 to 239, 0 to 351));

end image_read;

architecture Behavioral of image_read is

type img_array_t is array(natural range <>, natural range <>) of natural;
signal img_array : img_array_t(0 to 522, 0 to 447);

begin

recievedata: process
--variable img_array : img_array_t(0 to 239, 0 to 351);
---file img_file : text open read_mode"img.txt";


begin
load : text open read_mode "img.txt";
variable l : line;
variable temp : natural;
end;

for y in 0 to 522 loop

readline(img_file, l);

for x in 0 to 447 loop
read(l,temp);
img_array(x,y) <= temp;
end loop;
end loop;

end process;

end Behavioral;

ERROR:cannot continue because of fatal error


First i made a text file with the image pixel values.After that i simulate the code using modelsim 5.5...I got that error

You didnt post the error still - post the whole error.
Also - Modelsim 5.5 is very old (at least 8 years now).

- - - Updated - - -

Having another quick look - its probably because you have no waits in your process. It reads the image in zero time and then tries to read it again (and will keep reading it an infinite number of times in zero time). Im guessing its running off the end of the file. You need at least 1 wait in the process.

TrickyDicky said:

You didnt post the error still - post the whole error.
Also - Modelsim 5.5 is very old (at least 8 years now).

- - - Updated - - -

Having another quick look - its probably because you have no waits in your process. It reads the image in zero time and then tries to read it again (and will keep reading it an infinite number of times in zero time). Im guessing its running off the end of the file. You need at least 1 wait in the process.

Click to expand...

These are the errors while simulating my code using modelsim 6.3

# ** Error: D:/x code/Untitled-1.vhd(34): near "open": expecting "<=" or ":="
# ** Error: D:/x code/Untitled-1.vhd(41): (vcom-1136) Unknown identifier "img_file".
# ** Error: D:/x code/Untitled-1.vhd(41): (vcom-1136) Unknown identifier "l".
# ** Error: D:/x code/Untitled-1.vhd(44): (vcom-1136) Unknown identifier "l".
# ** Error: D:/x code/Untitled-1.vhd(44): (vcom-1136) Unknown identifier "temp".
# ** Error: D:/x code/Untitled-1.vhd(45): (vcom-1136) Unknown identifier "temp".
# ** Error: D:/x code/Untitled-1.vhd(49): near "process": expecting ';'

you forgot to declare load as a file.
you area also trying to access the non-existint file "img_file".

These errors are normally self explanitory - they are there to help you.

hi...
I read the text file. I want to write it in another text file..I wrote code for that.but it does not works....

This is my code for write the text file


process
file outfile : text open write_mode is "vit.txt";
variable outline : line;
variable temp : natural;
begin

write(outline, temp, right, 1);
--write(outline, "img", right, 16);
writeline(outfile, outline);


wait;
end process;

I didnt get any error...but not get output text file...please help

well, you should get something (0 should be written to the file).
Is this all of the code? Have you run the code?

TrickyDicky said:

well, you should get something (0 should be written to the file).
Is this all of the code? Have you run the code?

Click to expand...

yes...i got single zero after simulation in the text file....

This is my full code for read and write

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
use std.textio.all;
use std.standard.boolean;
--LIBRARY sim_util;
--USE sim_util.text_util.ALL;
--USE sim_util.conv_util.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity search is
--port( z : out std_logic_vector (2 downto 0));
end search;

architecture Behavioral of search is
type img_array_t is array(natural range <>, natural range <>) of natural;
-- signal img_array : img_array_t(0 to 29, 0 to 125);
signal img : img_array_t(0 to 4, 0 to 4);
constant a : integer := 0;
constant b : integer := 1;
begin
process
file img_file : text open read_mode is "val.txt";
variable l : line;
variable temp : natural;
variable z : natural;
begin


for x in 0 to 4 loop

readline(img_file, l);
--if (l = 5) then
--l := a;
--end if;
for y in 0 to 4 loop
read(l,temp);
--if temp < 8 then
--temp := a;
--else
--temp := b;
--end if;
img(x,y) <= temp;
end loop;
end loop;
wait;
end process;

process
file outfile : text open write_mode is "vit1.txt";
variable outline : line;
variable temp : natural;
begin
for x in 0 to 4 loop
write(outline, temp, right, 16);
for y in 0 to 4 loop
--write(outline, "img", right, 16);
writeline(outfile, outline);
--outline <= temp;
end loop;
end loop;


wait;
end process;

end Behavioral;

You're not assigning anything to temp in the second process, so you're going to write a load of zeros to the file.

TrickyDicky said:

You're not assigning anything to temp in the second process, so you're going to write a load of zeros to the file.

Click to expand...

I have changed my code into another way....The input text file i have given is an array ...but i got a single coloumn output in the another text file.....please help to change this code....

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use std.textio.all;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity rw is
end rw;

architecture Behavioral of rw is
type img_array_t is array(natural range <>, natural range <>) of natural;
-- signal img_array : img_array_t(0 to 29, 0 to 125);
signal img : img_array_t(0 to 4, 0 to 4);
constant a : integer := 0;
constant b : integer := 1;
begin
process
file img_file : text open read_mode is "val.txt";
file outfile : text open write_mode is "vit1.txt";
variable l : line;
variable temp : natural;
variable outline : line;
variable z : natural;
begin
for y in 0 to 4 loop

readline(img_file, l);
--if (l = 5) then
--l := a;
--end if;
for x in 0 to 4 loop
read(l,temp);
--if temp < 8 then
--temp := a;
--else
--temp := b;
--end if;
img(x,y) <= temp;
write(outline, temp, right, 1);
writeline(outfile, outline);
end loop;
end loop;
wait;
end process;
end Behavioral;

these are my input and output


input.txt
15 5 5 9 8

5 2 5 8 7

8 4 8 7 9

8 5 4 7 9

9 8 8 9 7

output.txt

15
5
5
9
8
8
8
8
8
8
5
2
5
8
7
7
7
7
7
7
8
4
8
7
9

- - - Updated - - -

TrickyDicky said:

You're not assigning anything to temp in the second process, so you're going to write a load of zeros to the file.

Click to expand...

I have changed my code into another way....The input text file i have given is an array ...but i got a single coloumn output in the another text file.....please help to change this code....

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use std.textio.all;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity rw is
end rw;

architecture Behavioral of rw is
type img_array_t is array(natural range <>, natural range <>) of natural;
-- signal img_array : img_array_t(0 to 29, 0 to 125);
signal img : img_array_t(0 to 4, 0 to 4);
constant a : integer := 0;
constant b : integer := 1;
begin
process
file img_file : text open read_mode is "val.txt";
file outfile : text open write_mode is "vit1.txt";
variable l : line;
variable temp : natural;
variable outline : line;
variable z : natural;
begin
for y in 0 to 4 loop

readline(img_file, l);
--if (l = 5) then
--l := a;
--end if;
for x in 0 to 4 loop
read(l,temp);
--if temp < 8 then
--temp := a;
--else
--temp := b;
--end if;
img(x,y) <= temp;
write(outline, temp, right, 1);
writeline(outfile, outline);
end loop;
end loop;
wait;
end process;
end Behavioral;

these are my input and output


input.txt
15 5 5 9 8

5 2 5 8 7

8 4 8 7 9

8 5 4 7 9

9 8 8 9 7

output.txt

15
5
5
9
8
8
8
8
8
8
5
2
5
8
7
7
7
7
7
7
8
4
8
7
9

yes. If you look at your code, you're writing each value to a new line. The writeline function appends a newline character after whatever is in outline.

you probably want to move the writeline outside of the inner loop, and change the write statement to:

write( outline, integer'image(temp) & " ");