even I said the same thing regarding clock transition limits . But the interviewer said the clock transition constraints are set by us.So There is no need of fixing every clock transition.Let us assume maximum clock transition limit is 100ps .
1)First of all who constrains this clock transition limit ? synthesis people or top level team?
2) if clock transition is above 120 , we need to fix for sure
3) If clock transition is between 110-120 , do we need to fix it
4) If clock transition is between 100-110 , do we need to fix it
The technology node is 28 nm tsmc.
Please help me in understanding this topic
Thanks
jaya sree