re : do we need to fix clock transition violation

[jaya sree]

Hi all ,

In one of the interview , I was asked :

do we need to fix every clock transition violation " ?

I replied yes.But it seems the answer is no . I was told to find out why ?

Please help me by answering it

Thank you
jaya sree

 

[vijay.mani884]

Well it depends, one the behaviour of the design. usually, it never happens. there are lot of timing exceptions which are included in the design so, I think the answer is "NO".

Cheers

 

[sam536]

YES. These clock transition violations need to fix. The timing is valid if below condition is met.

INPUT transition <= LIB transition.
Output Cao <= Lib cap value .

now its upto signing off team to risk the design or schedule .

Recommendation is to fix . Depends again on the magnitude and corresponding path Setup and hold slack values. Many factors involved here like, lib characterization?. Usually, because of these, hold violations will be hidden , so need to be careful.

Regards,
Sam

 

[yadavvlsi]

I totally agree with Sam. If you are exceeding library transition limit, your cell delay will not be accurate. When transition limit exceed library limit cell delays are extrapolated those might be inaccurate.

 

[jaya sree]

even I said the same thing regarding clock transition limits . But the interviewer said the clock transition constraints are set by us.So There is no need of fixing every clock transition.Let us assume maximum clock transition limit is 100ps .

1)First of all who constrains this clock transition limit ? synthesis people or top level team?
2) if clock transition is above 120 , we need to fix for sure
3) If clock transition is between 110-120 , do we need to fix it
4) If clock transition is between 100-110 , do we need to fix it


The technology node is 28 nm tsmc.

Please help me in understanding this topic

Thanks
jaya sree

 

[yadavvlsi]

I got your point now. Clock transition limit is defined by physical design team and it is specified in the clock specification file. Clock transition limit will be much smaller than library limit. We have tighter transition on clock to avoid crosstalk. In this case you need not fix every transition violations. You have to fix transition violations if it is exceeding library limit.

 

[vijay.mani884]

Well, the chip level guys/team will give you the specs, where in he will define all these things. then the implementation guys need to follow that even the PD guys. You will get to know all these through experience...

cheers

even I said the same thing regarding clock transition limits . But the interviewer said the clock transition constraints are set by us.So There is no need of fixing every clock transition.Let us assume maximum clock transition limit is 100ps .

1)First of all who constrains this clock transition limit ? synthesis people or top level team?
2) if clock transition is above 120 , we need to fix for sure
3) If clock transition is between 110-120 , do we need to fix it
4) If clock transition is between 100-110 , do we need to fix it


The technology node is 28 nm tsmc.

Please help me in understanding this topic

Thanks
jaya sree