RC delay line cascading problem

[Debdut]

Hi, I have the above RC delay line. Its purpose is to generate 1 ps delay at each stage. R values based on Elmore delay model. The 1st RC network is for generating a dominant pole and other 10 following networks are for generating 1 ps delays.
I want to generate a overall delay of 400 ps, but I cannot cascade 40 of this delay line to generate the delay. I tried using a diode for cascading, did not work. I also tried a high pass RC network to cascade two delay lines, also not working.

 

[zorro]

If starting from your first model you multiply all the R's by a factor Kr and all the C's by a factor Kc, then all the delays will result multipied by a factor Kr*Kc.
Consequences are:
= rise times will be multiplied by the same factor
= input and output impedances change
= values of R's and C's could result too high (but you can choose the best combination of Kr and Kc)

 

[Debdut]

Yes I understand. But I need 1 ps delay 400 times. Not just 400 ps delay.

 

[zorro]

Please state precisely the problem.
Do you need 400 simultaneous outputs at 1 ps apart, or a delay adjustable in 1 ps steps, or something else?

 

[Debdut]

zorro, You are right. I need 1 ps delays at every point of the RC network. And I have a RC network that generates 1 ps delays as such. But it is only capable of 10 such delays. I need 400 such delays placed 1 ps apart. So I was thinking of cascading 40 such networks.



Hey, I did the above and its working ok. However the transmission gate is consuming 6 ps. I had to short the BS terminals to reduce capacitance. But I don't know how will the body terminal MOSes appear in layout.

 

[BradtheRad]

Light travels 1/100 inch in 1 pSec. Therefore what if you were to send the signal through a length of wire 4 inches long, and tap it at 400 points? But perhaps that doesn't help toward a solution. I guess you want the waveform shape delayed, as well as its time of arrival?

- - - Updated - - -

Consider combining inductors (in series), between your capacitors. Such an LC network should lose less signal amplitude, and allow you to use more stages.

This simulation illustrates the concept.



The first scope trace is the input signal. Each LC stage delays the waveform a few pSec. You'll need to experiment to find the proper values for your project.

Notice some amplitudes are greater than the input signal. This is merely a simulation, and you may not get the same behavior.

 

[zorro]

...
Therefore what if you were to send the signal through a length of wire 4 inches long, and tap it at 400 points?
...
Consider combining inductors (in series), between your capacitors.
...

I guess that it is for an IC (is this right, Debdut?). In this case, those ideas would not be very suitable.

Assuming that you need to delay digital signals, I think you should place buffers between networks in order to restore the signal shape (rise and fall times).

 

[Debdut]

Yes, I cannot use many inductors as it will take too much space.

I think you should place buffers between networks in order to restore the signal shape (rise and fall times).

Buffers, do you mean digital buffers or source follower amplifiers as buffers. I have tried digital buffers using inverters, however thy are introducing some 100 ps delays. I want to try with source follower buffer and see what happens.
Any thoughts...

 

[FvM]

Cascading of large number of delay elements without intermediate buffers can work with lossless LC chains, hardly with lossy RC.

It's still unclear how you want to tap the delay line. Consider that any kind of buffer/sense amplifier or mux switch will affect the delay line behavior considerably. I fear you are showing only a small, probably lesser significant part of your design.

 

[Debdut]

I will tap the delay line at various points using transmission gates having small W and L so that they contribute least capacitance (attofarads).
I did the following and it is working. The numbers at different nodes denote delays in ps.

 

[zorro]

Some points are:

1) Without buffering, the slopes of the signal at great delays will be so slow that the time at which it crosses the logical level become too sensitive. This can bring incertitudes (variations) in the delay times and perhaps glitches.

2) With your last topology, buffers should be used as well. The problem with this topology is that delays could be non-monotonic. For example, delay at tap nominally 19 ps could be greater than delay at tap nominally 20 ps, even if buffers are used. Depending of the application, this can be a problem or not.

3) Debdut, what are the tests/simulations you perform in order to check that your circuits work?

 

[Debdut]

Yes I am having huge problems in tapping the line. The point I am tapping is experiencing large capacitance. I have to use different type of mux maybe cmos gate based mux. Cannot use tx gate based mux.

zorro - "Debdut, what are the tests/simulations you perform in order to check that your circuits work?"

I am trying with ideal resistors and capacitors. Then I will use resistors and capacitors from foundry library and see how the delays change. Then I will do the layout and see how the parasitics affect the delays.

 

[BradtheRad]

I tried a simulation of post #10.



Notice the waveform at 'out 1' coincides with 'out 5'. The second set of capacitors generates almost exactly the same amount of delay as the first set.

---------------------

I have not been able to let go of the idea of tapping into the innate physical delays along a length of wire. A waveform appearing at one end of a wire, will take 400 pSec (at the speed of light) to appear 4.7 inches distance down that wire. I cannot be certain it will work although I don't see why it should not.

 

[Debdut]

You can try removing the bottom 50 ohm resistance.

I have not been able to let go of the idea of tapping into the innate physical delays along a length of wire. A waveform appearing at one end of a wire, will take 400 pSec (at the speed of light) to appear 4.7 inches distance down that wire. I cannot be certain it will work although I don't see why it should not.

The capacitor problem I am facing is this-. The delay selectors are cmos transmission gates. The capacitors on each of the sides are Cgs+Csb and Cgd+Cdb.