rate mismatch between input data to output data

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win2010

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Hello,

I need to send 32208 bits of serial data within the 32128 clock per bit of input in VHDL.....

How to do this rate change between input and output...?

output has more data than input....
 

What? You want to send more data than you have? This violates the physical law of Conservation of Data.

I think you need to either restate your question or rethink your problem.
 

by taking 32128 bits of data i need to send 32208 bits of data...
Means, my logic generates extra 80 bits for input and send to next module...
32208 = 32128 + 80 bits of header
 

Without knowing more specifics of your system, the obvious way to handle this is to use a fifo. The way I would do it is to read in 8-bit chunks, write them to a fifo. You don't specify data rates, burst rate or anything else, so it's impossible to give any more information.
 


More specifics can be found in the other thread that the OP started...
https://www.edaboard.com/threads/311752/
...apparently he did not like either of the proposed solutions in that thread.

KJ

- - - Updated - - -

win2010 said:
Hello,

I need to send 32208 bits of serial data within the 32128 clock per bit of input in VHDL.....

How to do this rate change between input and output...?

output has more data than input....
Click to expand...

One solution is a dual clock fifo where the output clock is running at least 0.25% faster than the input clock.

KJ
 

I gave the OP more than one option, which should have been enough to get them started down the path to success.

What's that saying about the horse and water... ;-)
 

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