Random number generator sequence issue

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Trickedeasy

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Hi
Im implementing a random number generator using VHDL and Whether the seed are initialised to a particular number or left
uninitialised, for both cases, same sequence of random number are generated every time I restart the simulation.
I need random seed values after each cycle of random generation concludes. Please help me how can i do this.
P.S I need synthesize-able code advice.
Thanks in advance.
 

Re: Random number generator sequence issue. Please help

are you using LFSR?
 

Re: Random number generator sequence issue. Please help

Yes I did use LSFR and I could generate random sequence.
 

Re: Random number generator sequence issue. Please help

If you were using verilog I would have suggested seeding the registers of the LFSR with a $random value. As you are using VHDL I suggest trying to use modelsim's signal spy to access the LFSR register and seed the registers with VHDL's equivalent to $random.

Otherwise you'll have to modify your LFSR so you can load a start value and add code to allow your internal control bus to load a seed value. Then at the test bench level you will perform write(s) to load the LFSR with a random start value. In this case the loadable start value will be available after synthesis.

regards
 
Re: Random number generator sequence issue. Please help

@ads-ee sorry but I have no idea what you mean by this "Then at the test bench level you will perform write(s) to load the LFSR with a random start value. In this case the loadable start value will be available after synthesis.". Could you please explain elaborately.
Regards
 

Re: Random number generator sequence issue. Please help

I can suggest some ways. but this way needs external resources.


1) use an EEPROM and store the LFSR values in it to be used in next start up.
2) use analog noise generators and sample them in start up.
3) use an external Time generator IC and use it's value as a seed.
 

Re: Random number generator sequence issue. Please help

well my typical test bench has a bus functional model (BFM) of a uC so I use that transactor to generate writes to my internal FPGA registers. So in my case I could easily make a loadable LFSR and use the test bench uC BFM to load the LFSR with different values. If you don't have something like that in your test bench then you could always run a load signal and the LFSR load data to the top level of your design and make it part of the I/O of your top level so you can load it from the test bench.
 
Re: Random number generator sequence issue. Please help

@Trickedeasy
Whether the seed are initialised to a particular number or left uninitialised, for both cases, same sequence of random number are generated
Click to expand...
I think this is not true for a LFSR generator. probably you could not load your LFSR correctly or mot simulating enough time.

I need random seed values after each cycle of random generation concludes. Please help me how can i do this.
Click to expand...
you can use another LFSR to load this LFSR with random seed when starting it.

In the last post of myself, I was think that each cycle of random generation concludes with powering off the FPGA.
 
Re: Random number generator sequence issue. Please help

Sorry was not around for some time. Will try all your suggestions and get back to u
regards
 

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