Random Noise of Charge Pump - Theoretically

[gviva_2k]

Hello All,

Does anyone know how the calculate the Random noise generated by a charge pump theoretically?

We all know that, wider the up and down pulses in the locked state of a PLL (To avoid deadzone), more the charge pump noise integrated onto the loop filter. However, how do we arrive at a theoretical expression for this noise?

To put it in other words, what is the theoretical value of noise in a charge pump that creates random jitter in a PLL, if all the other components are ideal. (Say VerilogA models)

 

[love_analog]

Take Icp (noise) of pmos and nmos, rms them together

I*Z gives you the voltage noise. You can convert to input phase noise etc.

Better to go to designer-guides.org and read about it.

 

[gviva_2k]

Hello.. Thanks for the response.. I shall also take a look at designers-guide