RAM: rising edge detection not working

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity ram_ent is
port(addr:in std_logic_vector(3 downto 0);
    addr_in:in std_logic_vector(3 downto 0);
    data_in:in std_logic_vector(7 downto 0);
    ram_write:in std_logic;
    enter:in std_logic;
clock:in std_logic;
ram_enable:in std_logic;
dout:out std_logic_vector(7 downto 0));
end ram_ent;

architecture ram_arch of ram_ent is
type ram_arr is array(0 to 15)of std_logic_vector(7 downto 0);
signal tmp_ram:ram_arr;
begin
process(clock,ram_enable,ram_write,enter)
begin
  if  ram_enable='1' and ram_write='0' then
if (clock'event and clock='1') then
dout<=tmp_ram(conv_integer(addr));
end if;
elsif ram_enable='1' and ram_write='1' then
if (clock'event and clock='1') then
if rising_edge(enter) then
tmp_ram(conv_integer(addr_in))<=data_in;
end if;
end if;
end if;

end process;
end ram_arch;

if rising_edge(clk) then
  enter_r <= enter;

  if enter = '1' and enter_r = '0' then --rising edge on enter
    --write to memory