salma ali bakr
Advanced Member level 3
Hi,
I'm doing Equivalence Checking between the RTL and the Netlist of a design, which has 4 RAM IPs. Of course, I can't use the behavioral HDL models of the RAMs since they're only used for simulations! So, what should I do now in order to verify the design?! Should I mark the RAMs as black boxes, or just use their interfaces?! Or maybe just load them as db files?! I'm totally confused about what I should do, and I've tried a lot with different scripts but in vain! So any ideas or sample scripts would be GREAT
By the way, I'm now using Synopsys Formality but I can switch to Cadence Conformal.
Thanks in advance and regards,
Salma
I'm doing Equivalence Checking between the RTL and the Netlist of a design, which has 4 RAM IPs. Of course, I can't use the behavioral HDL models of the RAMs since they're only used for simulations! So, what should I do now in order to verify the design?! Should I mark the RAMs as black boxes, or just use their interfaces?! Or maybe just load them as db files?! I'm totally confused about what I should do, and I've tried a lot with different scripts but in vain! So any ideas or sample scripts would be GREAT
By the way, I'm now using Synopsys Formality but I can switch to Cadence Conformal.
Thanks in advance and regards,
Salma