Race condition check in Verilog

verilog rs latch

Hi,

Is there a way to check for race conditions in Verilog?
For e.g., I implement an RS latch using nand gates. The situation in which both the inputs are 0, the outputs q and qbar both will be 1, which is a violation of the definition of a latch. Does Verilog point out such errors? Or would I have to simulate the circuit and check to see situations in which both q and qbar are 1?

Thank you.

definition of verilog race condition

race condition is one which is sensitive to the order in which the simulator executes events, but that order is not well-defined. That is, if two events occur at the same instant of simulated time, the behavior of the model is different depending upon which is executed first, but the order of event execution is not defined by the language

It is relatively easy to write code which is sensitive to event ordering, especially when writing behavioral models. Debugging models with race conditions is often difficult, because sometimes they work as intended, and sometimes they do not. Their behavior can change due to seemingly unrelated changes in other parts of the model, or by being run by different Verilog simulators

non blocking verilog race

Hi Gharuda,

gharuda said:

race condition is one which is sensitive to the order in which the simulator executes events, but that order is not well-defined. That is, if two events occur at the same instant of simulated time, the behavior of the model is different depending upon which is executed first, but the order of event execution is not defined by the language

Click to expand...

This is something interesting you've brought up; it has been gnawing at the back of my mind for quite some time. I am a Verilog novice and had uptill now assumed that as long as you didn't insert a delay between assigning values to variables, they would be executed at the same time. Does this hold?

Well another thing- Does the order in which you assign values to regs, or for that matter the ordering of statements in between the variable declarations and endmodule statement, affect the simulation result ? Palnitkar says it doesn't. I tried it in a code and it didn't seem to. If it doesn't, then the order in which the simulator executes the events is independent of the order of the code, and that order as you say is not well-defined. If this is so, any pointers to what determines the order in which these events are executed?

It is relatively easy to write code which is sensitive to event ordering, especially when writing behavioral models.

Click to expand...

I haven't come to behavioral modeling yet (started out with gate level). Is there any way I can put together a code in gate level that is sensitive to event ordering?

verilog schedule 2 event at same time

it depends upon the assignment statement your using

blocking "=+ or non blocking statements "<=".

their is inertial and transient delay while a expression is evaluated and assigned to a LHS variable. if u don't specify any delay then inertial delay is taken into account.

if blocking statement are used the the expression on RHS is evaluated and assigned to LHS variable and the next statement is executed .

in non blocking statement the expression are evaluated and they are assign at the end of simulation time.