[SOLVED] Qustion: Hold-time and propagation-delay.

[ammar_kurd]

Hello everyone,

In the book "Logic and Computer Design Fundamentals by M.Morris Mano and Charles R.Kime", after defining what a hold-time is and what a propagation-delay is, it is said that "Since Changes of the outputs are separated from the control by the inputs, the minimum propagation-delay time should be longer than the maximum hold-time "

This is related to the edge triggered flip-flop.

I don't get this, how is it so? can someone explain.

Thanks in advance.

 

[ted2]

Frankly, I think there might be a mistake in the book, as usually on a data sheet we find MINIMUM hold time - meaning how long the data has to be stable after the active clock edge. Also , usually the MAXIMUM propagation-delay time is specified.

Interchanging the two terms makes at least more more logical sense, as a D-flip-flop is a feedback device, where the output is fed back to the input, to keep the next (possibly new, if changing) state stable.

 

[ammar_kurd]

It is true what you said about hold-time, but how this is related to propagation delay, and are you sure it is a mistake? I will look for the errata and get back to you.

 

[vianychandru]

The specified is true in terms of a flop to flop interaction.

Consider two edge triggered flops using the same clock. If the launch flop's signal arrives earlier than the hold time of the capture flop, the capture flop might be latching on to a data which was to be captured in the next clock cycle or get into a meta stable state due to hold violation. To ensure this scenario does not occur, it is necessary to check if propagation-delay is longer than the maximum hold-time.

 

[ted2]

To fully understand potential complications with flip-flops one has to have some understanding how they are constructed: They have usually multiple "latches" (simple bi-stable loops with feedback, usually drawn as two NAND gates with crossing feedbacks)

A typical edge-triggered flip-flop is like this:

There are three interconnected latches, each consisting of two NAND gates. When you also consider, that each gate has at least some delay from inputs to the output, the circuit is getting very interesting!

Such feedback systems with delays are inherently sensitive to timing violations, as a latch will not reliably change its state, if the timing is marginal. There the propagation delay and hold time meet each other: In every feedback in very latch. Such systems behave predictably only when the input signal timing is in right relation to the propagation delays. If you google for instance "flip-flop metastability" you will find one bit weird thing going often wrong, when violating the timing requirements.

I leave detailed analysis to anybody interested enough. I have done such exercises many years ago, but feel a bit lazy today to repeat that