saulbit
Member level 4
I have designed two phase locked loops, one of which is covering from 1900M~3200MHz (VCO is from Z-comm,V600ME20) and the other is for a single frequency point for 1900MHz (VCO
is from Z-comm too, V603ME) on the F4 PCB. The PLL synthesizers are both HMC700 chips. Now the pll can be locked successfully. However, when I shaked the shieding box in which the two loops are
installed, the phase noise of the two loops began to get worse and to remain the terrible phase noise after stopping the shaking. There began to be some spurs distributed about a few
hundred Hz. I have tried several ways about the reference, such as OCXO and the signal generators from agilent company,ri and I also tried different phase detector frequency, varing from
10MHz to 50MHz, and I also tried the power supplies in th DC source and the switch sources, all of which got the puzzling state described above. So would anyone could bring me some
suggestions? Any reply is welcome.
is from Z-comm too, V603ME) on the F4 PCB. The PLL synthesizers are both HMC700 chips. Now the pll can be locked successfully. However, when I shaked the shieding box in which the two loops are
installed, the phase noise of the two loops began to get worse and to remain the terrible phase noise after stopping the shaking. There began to be some spurs distributed about a few
hundred Hz. I have tried several ways about the reference, such as OCXO and the signal generators from agilent company,ri and I also tried different phase detector frequency, varing from
10MHz to 50MHz, and I also tried the power supplies in th DC source and the switch sources, all of which got the puzzling state described above. So would anyone could bring me some
suggestions? Any reply is welcome.