Quick (and easy) question about Verilog / UCF editing

Hello,
what is the difference between writing:
NET "leds[0]" LOC = "U18" | IOSTANDARD=LVCMOS25;
NET "leds[1]" LOC = "M14" | IOSTANDARD=LVCMOS25;
NET "leds[2]" LOC = "N14" | IOSTANDARD=LVCMOS25;
NET "leds[3]" LOC = "L14" | IOSTANDARD=LVCMOS25;
NET "leds[4]" LOC = "M13" | IOSTANDARD=LVCMOS25;
NET "leds[5]" LOC = "D4" | IOSTANDARD=LVCMOS25;
NET "leds[6]" LOC = "P16" | IOSTANDARD=LVCMOS25;
NET "leds[7]" LOC = "N12" | IOSTANDARD=LVCMOS25;

and

NET "leds<0>" LOC = "U18" | IOSTANDARD=LVCMOS25;
NET "leds<1>" LOC = "M14" | IOSTANDARD=LVCMOS25;
NET "leds<2>" LOC = "N14" | IOSTANDARD=LVCMOS25;
NET "leds<3>" LOC = "L14" | IOSTANDARD=LVCMOS25;
NET "leds<4>" LOC = "M13" | IOSTANDARD=LVCMOS25;
NET "leds<5>" LOC = "D4" | IOSTANDARD=LVCMOS25;
NET "leds<6>" LOC = "P16" | IOSTANDARD=LVCMOS25;
NET "leds<7>" LOC = "N12" | IOSTANDARD=LVCMOS25;


?

Thank you very much

There should be no difference. At least not that I know of.