questions related to asynchronous design?

verylsi said:

Hi all,

Recently I was into an asyncronous design..
I have some question in mind..

What will happen if I write rising_edge(some_signal) to capture the transition?
I know the synthesizer will consider this signal as a clock .. and this design is completely asyncronous.
What effect will that make in implementing such designs?

also
If I assign a signal asynchronously for eg.-

signal temp_storage : std_logic_vector(3 downto 0) ;
begin

temp_storage <= input_signal( 3 downto 0);

end;

will this temp_storage stores a value.. as it is not inside a clocked process , it cannot be a flipflop.
Then what it will be? a latch ?
or i wont store anything at all.

I checked in simulation , it stores the value, but I am not sure in terms of hardware.

Please dnt mind the syntax error , I just wanted to explain my question.

Thanks in advance.

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What will happen if I write rising_edge(some_signal) to capture the transition?

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