Questions regarding type matching in VHDL

I have several questions regarding type matching in VHDL.
1. If one component outputs signed signal (i.e. 5-bit wide) and the main code accepts it as input port, how do I declare the port?

can I do it as:
or should it be inputted as std_logic_vector and then converted to signed format as:

2. If are the input ports, then can I do that:
or signed needs a std_logic_vector type operand to be a valid statement?

or maybe I should use TYPE_NAME' :

Thanks for the help

Re: types in vhdl

1. It really doesn't matter... however you like to code, either way seems fine to me. Just include the right libraries. I'd go for the top statement, because it saves me some lines in the code.

2. First of all, std_logic doesn't have signed or unsigned attributes. If you want to convert a 4-bit std_logic_vector to signed or unsigned forms, you can do that, but not std_logic to 4-bit signed or unsigned type.

As long as you do conversions of the same length, you can perform the conversion with the right libraries: unsigned, signed, std_logic_vector, integer, etc.

types in vhdl

what about the last line of code? I ment to convert 1-bit to 5-bit format and then used SIGNED' function to create 2's compliment of 5-bit number.

I was thinking to do that bacause I wanted to convert data stream consisting of ones and zeros to -1/1 format ... so I needed signed representation.

Maybe I should use IF statement instead to accomplish that? something like: ?

thanks

Re: types in vhdl

instead of writing these statements...just invert MSB acodring to "data" signal/ variable. because u do now ur "datasigned" value...

types in vhdl

ok

Also, I think I can I use integers instead of binary representation and then convert it to signed vector format:

Whould it be correct as well?

Thanks

Re: types in vhdl

i m not sure about synthesis issue with ur + and - sign... but i think u can use it.

Re: types in vhdl

You stick with a superset type such as std_logic_vector or subtype such as bit_vector and avoid conversions from one type to another.

Re: types in vhdl

delay said:

You stick with a superset type such as std_logic_vector or subtype such as bit_vector and avoid conversions from one type to another.

Click to expand...

Do you mean to use std_logic_vector to represent signed numbers in 2's compliement? What library do I have to use then and what not to?
I've read that std_logic_unsigned will make all std_logic_vector types unsigned. I guess I have to use numeric_std instead. But then I would have to remove std_logic_arith, right?

Here is the point of confusion:
What's the result of std_logic_vector(signed number in 2's compliment) using ieee.std_logic_arith VS ieee.numeric_std? is there a difference

<Also, found my mistake.. 11111 in 2's is -1, and 00001 is +1, (not 01111 as I used before).>

types in vhdl

anyone? maybe let me refrase my questions.

I am using signed type throughout my program. Now, there is one third party function that outputs std_logic_vector, that I have to use. The function looks like its std_logic_vector signal is in signed format (the sine wave with positive and negative values). 1. Can I just assume that it's in 2's compliment format similar to signed? In other words, how does STD_LOGIC_VECTOR holds signed numbers?

2. I understand that if I would like to match it to my internal signals, I would have to cast that signal to SIGNED. So, can I do SIGNED(STD_LOGIC_VECTOR signal) to do that? What would be the result of the above statement? Would it take the signal inside and convert it to 2's comliment? That would be useless for me if the signal is already in 2's compliment. If that's not correct, please let me know how can go around this.

3. I suppose STD_LOGIC_VECTOR can hold any format (1's, 2's or just magnitude) as long as you keep in mind in which context you are using it. However, the moment you start using SIGNED function, how does VHDL compiler recognize the numbers from then? Does it still treat them as STD_LOGIC_VECTOR and 'makes a note' for itself that it contains 2's compliement?

4. I've read that ieee.std_logic_arith and ieee.numeric_std are mutually exclusive libraries that you cannot use at the same time. Maybe using one or another one would somehow answer my questions above..

Re: types in vhdl

neocool said:

anyone? maybe let me refrase my questions.

I am using signed type throughout my program. Now, there is one third party function that outputs std_logic_vector, that I have to use. The function looks like its std_logic_vector signal is in signed format (the sine wave with positive and negative values). 1. Can I just assume that it's in 2's compliment format similar to signed? In other words, how does STD_LOGIC_VECTOR holds signed numbers?

2. I understand that if I would like to match it to my internal signals, I would have to cast that signal to SIGNED. So, can I do SIGNED(STD_LOGIC_VECTOR signal) to do that? What would be the result of the above statement? Would it take the signal inside and convert it to 2's comliment? That would be useless for me if the signal is already in 2's compliment. If that's not correct, please let me know how can go around this.

3. I suppose STD_LOGIC_VECTOR can hold any format (1's, 2's or just magnitude) as long as you keep in mind in which context you are using it. However, the moment you start using SIGNED function, how does VHDL compiler recognize the numbers from then? Does it still treat them as STD_LOGIC_VECTOR and 'makes a note' for itself that it contains 2's compliement?

Click to expand...

Your 3rd point seems close to perfect. SLV (Std_Logic_Vector) is a mere "collection" of bits, can mean any thing - signed/unsigned/2s complement etc. The numeric_std package was introduced to clarify this very problem. So use SIGNED for your arithmetics, use SLV to pass across modules - do the type conversion as you go along.

A VHDL compiler should recognize the signals as per their data type declarations.

Does that help?
Ajeetha
http://www.noveldv.com

types in vhdl

Thank you, that helped to clarify things. I figured as well that slv is used to pass between modules because the compiler did not like when I created signed port. I saw several examples on the internet that created signed port though.. but maybe it was just a mistake.

Also, as I understood, signed() and std_logic_vector() are basically used inside modules to CAST data (let the compiler know what type it is), and not actually convert data in terms of modifying the bits.
If you want to convert integer <==> slv then you can use to_integer and corresponding to_... for slv.
Is there a function to convert from unsigned to 2's compliement (modify the bits?) or just flip them yourself and add one?

Thank you

Confused with libraries

-edited by me-
created a separate topic
thank you