John Xu
Member level 3
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hysterisis comparator
hi,
We desiged a hysterisis comparator with 0.25um TSMC process. The target hysterisis of comparayor is 17mV.The circuit utilized is the well known topology as attached. The silicon test results on hysterisis is as below:
********
VTRP+ VTRP-
sample 1 0.906 0.898
sample 2 0.906 0.898
********
The refernce level is 0.9mv. From the results, we can see that its hysterisis is only 8mv and the obvious unsysmetry for the two trip points. We doubt that the mismatch caused it. But we have used the centroid technique in layout for those paired device and also you can see that we used large size to improve matching. Then why so serious performance degradation? This comparator is a key part in our system. So the accuarcy is important for us.
Would you give us some advice on this issue?
Thanks in adavnce
hi,
We desiged a hysterisis comparator with 0.25um TSMC process. The target hysterisis of comparayor is 17mV.The circuit utilized is the well known topology as attached. The silicon test results on hysterisis is as below:
********
VTRP+ VTRP-
sample 1 0.906 0.898
sample 2 0.906 0.898
********
The refernce level is 0.9mv. From the results, we can see that its hysterisis is only 8mv and the obvious unsysmetry for the two trip points. We doubt that the mismatch caused it. But we have used the centroid technique in layout for those paired device and also you can see that we used large size to improve matching. Then why so serious performance degradation? This comparator is a key part in our system. So the accuarcy is important for us.
Would you give us some advice on this issue?
Thanks in adavnce