questions on place and route.

[Abbigeri]

below are some questions on Place and Route,anyone who know the answers please do post a reply.

1. What is the reason for flipping the cell rows.

2. When you need to leave a gap in between the cell rows, how do you determine the height of the gap.

3.why core power pads should not be connected to the core power rings in the last.

4. if you are to use both vertical and horizontal stripes, what are the considerations to decide which one should be added to the power plan first.

5. how do you find out all the requirements of the clock tree.

6. purpose of filler cells.

7. the filler cells usually have widths that are given as 1x, 2x, 4x, 8x, etc the next bigger filler cell always has its width doubled why?

8. why is it better to insert the filler cells after detailed routing.

9. why physical verification can detect DRC and LVS violations that are not detected by the P&R tool.

10. STA passes but the simulation fails on the same logic path. reason?

11. simulation passes but STA fails on the same logic path. reason?

12. the timing requirement of a desing is met after the physical synthesis step. clock tree synthesis is then performed and all the clock trees meet the skew and latency specifications. however , STA shows that there are many timing paths with
very poor timing slack. reason for poor timing slack?

thanks

 

[asic_world]

9. why physical verification can detect DRC and LVS violations that are not detected by the P&R tool.


I think ~~ physical information is nt merged in pnr stage.... verification needs to be done for finding extra devices formed

 

[rakesh1234]

1. In order to save area we abut the two cell rows so the common power and ground is shared by the cells. so we are fliping the cell rows.
2.If a horizontal routing resource is not enough we are providing the gap between the cell rows in order to provide somre extra horizontal routing resource in metal1. The gap is determined by the metal1 minimum spacing rule.
6.Filler cells fill gaps between pad cells and provide routing between them.
8.beacuse at this time the cells are well placed and the location of the cells are fixed. That we are not going to change the cell pllacement. So we can know the exact location of the filler cell. So we are inserting the filler cells after the detailed routing.

I know only this

 

[p_shinde]

form my side..

4. start from lowest metal.....(if i am rgt) just think hw many vias u would drop on...
6. filler cells r inserted while creating rails......to have continuous rails..
7. its not only those........i have even came across 1x, 3x, 5x, so must be depending on the library.........


thanks,
Prasad

 

[nav_vlsi]

5. SDC obtained after systhesis must give u prorper idea abt clocks in design
8. since filler doesnt affect timing, there is no need to add them in earlier stages of routing.
9. Most of P&R tools look only at the metal layer present in std cells,they are not much botherd about (OD, active or diffusion layer). with only metal info visible it may be possible for them to check for LVS issues

 

[lovelytwq]

3.core power pads should be connected to the core power rings in floorplan