Questions on I2C clock and SCL

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Hi all,
For a i2c salve, any friend got the idea of using SCL signal as the trigger clock instead of using a higer frequence inner clk?
I mean why don't use SCL pin as the asynchronize clock? So we can save the inner clk to sample the SCL and SDA signals. Is there any risk?
Thanks!:razz:
 

Bad idea,

1. You'll have to have at least one clock in your system in order to generate the SCL in the first place.
2. The SCL runs only when a transaction takes place. It's a stable '1' when the bus is idle.

---------- Post added at 09:24 ---------- Previous post was at 09:23 ----------

Please share your reason to do that.
There may be more elegant solutions
 

Thank you!
1. You'll have to have at least one clock in your system in order to generate the SCL in the first place.

The SCL is generated by master, so I don't need the clock in the slave system.

2. The SCL runs only when a transaction takes place. It's a stable '1' when the bus is idle.

Yeah.
So I think when the transaction taking place, the rising or falling edge can be used as trigger to sample the SDA. Therefore, as slave device, I don't need another clock.
 

some questions rises:
1- how do you detect the start condition? SDA fall when SCL='1'?, same idea for the restart & stop condition?
2- multi-master mode?
3- strengh SCL line?
 

Simple I2C slave devices are working exactly the way you assumed. In so far it's surely possible. They need some typical asynchronous means, e.g. glitch filters for operation complying with the I2C spec. If your design is a simple one and has no other need for a clock, the consideration seems plausible. When working with programmable logic, you're probably missing the means to implement glitch filters. And the synthesis tools are not supporting asynchronous design very well.
 

Thank you all!

Yes I think I need some glitch filters. As for programming ways of digital design, can I connect delay units to SCL, and use the output of delay units as clk for dff, thus filter the glitch?
 

In addition the asynchronous logic must be able to accept slow rise-times according to the I2C specification. Most likely, a schmitt-trigger is required after the glitch filter to achieve this.
 
hello friend,
*PLEASE explain the concept of CLOCK STRECTHING and wait management.

*And what's the need of clock streching in I2C while there is acknowledement

And also explain the funda of ACKnowledgement in case MASTER is readind from slave.
 

As the I2C bus uses open drain output,
The receiving slave can hold the SCLK line low in order to prolong the transaction (in case it's busy...)

You should note that, even though clock streching is a part of the I2C standart - it's rarely used. So is 10 bit addressing and arbitration.

As to a master ACK from slave - the concept is very simple. As the master receives data from a stave, it must drive the SDA line low. This tells the slave that data has been received by the master.
 
The master indicates to the slave during the read frame with a nak, that the end of the frame.
The clock stretching could be used between each bit or between the byte and the ack bit, when the protocol i2c is completely made by software which act on gpio pads.
 


What do you mean by SLAVE BUSY...???

And Please Elaborate the concept of clock strecthing by taking some example....EXACTLY WHEN DOES IT OCCUR (clock stretching)??
 

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