Questions of Pipeline ADC design

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carlyou

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If I want to design a 12bit, 65 or 80MHz pipeline ADC, how can I get the various modules' parameters, such as the sample resolution, OTA gain, and so on, who can give me a advice or introduce some papers? For some reasons, I have to use hspice in windows to simulate my design and only have a TSMC .35 level49 model, is it enough to achieve my aim? Thanks very much.
carl
 

Maybe you can read these papers as following:
‘A pipelined 5-Msample/s 9-bit analog-to-digital converter’
‘Optimizing the stage resolution in pipelined, multistage, analog-to-digital converters for video-rate applications’
‘A 10-b 20-Msample/s analog-to-digital converter’
‘Indirect testing of digital-correction circuits in analog-to-digital converters with redundancy’
The author is Lewis and the method of time-interleaved can be included in this project.
 

tsmc 0.35um Process ,, It is a little hard ,
We have implement 80M/12bit pipeline ADC ,
We use 0.18um process , almost MOS we use .35um , but in the critical part we use 0.18um MOS , Like OTA . That OTA can get more high gain . high BW
 


want to desig pipeline adc:
by using cadence tool
can u help me or send schematic diagram of each block, darshana26kuche@gmail.com
 

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