Questions:Lower Node Technology

These are few questions:

1.In 28nm tech, HKMG technology is used, i.e, instead of using PolySi they use metal for gate. Its given that it helps adjust the gate to low threshold voltage. How?
2.Channel length is reduced and kept at particular nodes, say 180nm,130nm and so on. How is this particular node decided?
3.Except for area , is there any other advantage of STI over LOCOS?
4.Variation of drain saturation current is more for 28nm tech. How is it useful?
5.Why is Cu used for vias in 28nm tech?
6.What is poly spacing effect?
7.High sheet resistance reduces threshold voltage. How?
8.Why are spacers of silicides used?

Thanks in Advance.

2.Channel length is reduced and kept at particular nodes, say 180nm,130nm and so on. How is this particular node decided?

This is just to keep pace with the Moore's law, number of transistors double every 18 months. Other way of looking at this, if it took 100mm^2 for a chip now, it would take 50mm^2 after 18 months. If area is halved, the length should reduce by 0.707.

180*0.707= 126
130*0.707 = 90

pradeeppiskala said:

Other way of looking at this, if it took 100mm^2 for a chip now, it would take 50mm^2 after 18 months. If area is halved, the length should reduce by 0.707.
0

Click to expand...

Hi Pradeep,

I agree with the reducing is due to pace with Moore's Law. Thank you for the post.
Can you show how did you deduce If area is halved, the length should reduce by 0.707 scientifically.

Thanks in Advance,
Prashanth

Let X one of the side of old technology and Y be the side of the new tech node. Area relation between two nodes is X^2=2*(Y^2) => Y=1/sqrt(2)=0.707

ok. Still to get more clarity.

Are you measuring A=L*B ? and If so When you substitute How the X and Y will get squares?
Are you calculating L = B?

Can you name it conventionally.Eg:Areaold Areanew Lengthold Lengthnew Widthnew etc

This is considering a square shaped chip

Yes I Agree. What I am saying is Whether you have made Length = Breath ?.

Am not able to get X^2=2*Y^2?

If you have any link or article on the same, please share it.
Or, Please deduce it with explanation.

1. Threshold voltage in a given technology depends on the gate insulator thickness & its dielectric constant. Lesser the thickness, less threshold voltage. There is a limitation in decreasing oxide as it will increase in gate leakage due to tunneling. It is a reliability issue. Threshold voltage is inversely proportional to dielectric constant. So with high-K material, we can have low threshold voltage, still having more thickness. Metal have very less resistance compared poly-Si. So there will not be any drop across the metal gate. This also will help in reduction of threshold voltage.

https://en.wikipedia.org/wiki/High-k_dielectric
https://en.wikipedia.org/wiki/Threshold_voltage

2. We see 90nm, 65nm, 45nm, 32nm, 22nm technology nodes.These technology nodes are decided by dividing the previous node by square root of 2. So that number of components remains the same even after reducing the area by a factor of 2 (because length is divided by square root of 2 so area will be divided by 2 ).

3. The main advantage of STI over LOCOS is area reduction. Another advantage is alignment tolerence reduction.

4. Variation of drain saturation current is more for 28nm tech.? This question is not clear to me. But drain current in 28nm drain is more. Drain current is
inversly proportional to channel length.

5. Copper has resistance to electromigration, the process by which a metal conductor changes shape under the influence of an electric current flowing through it and which eventually leads to the breaking of the conductor, is significantly better with copper than with aluminium. This improvement in electromigration resistance allows higher currents to flow through a given size copper conductor compared to aluminium. The combination of a modest increase in conductivity along with this improvement in electromigration resistance is to prove highly attractive.

6. Poly Space Effect: The distance between gates including dummy poly has a direct effect on the drain current of the transistor.Poly Space effect is the change in the saturation current of a MOS device due to presence of a poly near to the Gate.

Thanks Yadav.

Few more clarification required:
1.because length is divided by square root of 2 so area will be divided by 2
Can you prove it? L cannot be equal to B. Here Length is Poly length. I am not satisfied with the answer.

2.alignment tolerence reduction
Brief about this. Also, send some link on the same topic.

3. On question 4:I will get back to this. Here variation I mean, the slight fluctuations. Is it useful?
Have read it, can't recall it.

4.PS Effect:Here when you say poly near a gate, Are you saying a transistor with poly routed paralleled with gate? or kind of fingers?
Send some link on the same topic.


Thanks in Advance.