questions in verilog-a,

[arsenal]

hi, i have declared internal bus in verilog-a as:
electrical [0:262143] cur_a;
...
however, an error is reported in simulation as
" Incompatible bus declaration for "cur_a"
Illegal access "cur_a[8466],
Array index outside the declaration range."

then can someone tell me what is wrong? thank you very much.

 

[willyboy19]

As far as I know, you can not define a bus in Verilog-A. Even you can, you may already exceed the range a legal bus can declare.

 

[svensl]

This should work:

module 3bitBus(a,b,c,out);
input a,b,c;
output [0:2] out;
electrical a,b,c;
electrical [0:2] out;

 

[cooldog]

Hi there,

Verilog-A is not well defined language. There is no bus concept for analog part. If the vador tool supports bus port like svensl said, it should work. I don't know if Cadance Spectre support bus port issue. But some other tools support, like hsim, adit ... So this is the vador issue.

 

[andy2000a]

I never use verilogA or VHDL_AMS for real design ,
I ever use matlab for analog behavior ,
but for Mix mode SOC design ,
in gerneal , analog block design by analog RD , digital is by digital RD ,

project leader simulation whole chip by hsim/nanosim , but
none use beahvior sim in Top level as I know .

like Saber , Dolphin smash .. support analog + digital design ,
but project leader only use "hsim or powerMill" tool .

Have any fabless design use RTL_a ? I don't know .