Questions about width of addition and overflow

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Flo89

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Hello experts,

When I try to synthesize the following code:

Code: 
variable sin_temp, cos_temp,sin_tempn, cos_tempn : sfixed (1 downto -14);
sin_tempn := sin_temp - (cos_temp srl i);

I get this error:
Width mismatch, location has width 16, value 17

But because of the amplitude of sin and cosine beeing max. 2 in normalized form there should be no overflow because the algorithm is there to calculate sin and cosine values.
The problem is that this code is in a loop and so I cannot simply spend 17 bits for the result because then I would need 18 for the next cycle of the loop.
How to handle this?

Thanks in advance for help!
Florian
 
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The addition and subtraction functions in the fixed pkg return a result with 1 more bit by default. The easiest answer will be to create another variable with the extra bit then trim it into sin tempn.

A question on your design through, why are you using a for loop and why using variables. From your code in guessing the result is going to be rather slow without pipelining.
 
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    Flo89

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Thanks for the fast reply.
Perhaps I insert the code snippet an you could give me an advice about the pipelining? I thought about that but because it's my first VHDL project I'm not quite familiar with that and would be glad about any help for this kind of stuff!

Code: 
variable di: std_logic;
	variable z : std_logic_vector (PA_RES DOWNTO 0) := (others => '0');
	variable sin_temp, cos_temp,sin_tempn, cos_tempn : sfixed (1 downto -14);
		begin
		if(rising_edge(clk) and (enable_cordic='1')) then
				z := phase;
				sin_temp := sin_init;
				cos_temp := cos_init;
				sin_tempn := (others => '0');
				FOR i in 0 to 12 LOOP
					if (z(PA_RES)='1') then
						cos_tempn := cos_temp + (sin_temp srl i);
						sin_tempn := sin_temp - (cos_temp srl i);
						z := std_logic_vector(signed(z) + signed(my_Rom(i)));
					else	
						cos_tempn := cos_temp - (sin_temp srl i);
						sin_tempn := sin_temp + (cos_temp srl i);
						z := std_logic_vector(signed(z) - signed(my_Rom(i)));
					end if;
				cos_temp := cos_tempn;
				sin_temp := sin_tempn;
				END LOOP;
		cos <= std_logic_vector(cos_temp);
		sin <= std_logic_vector(sin_temp);
		end if;
	end process cordic;

phase is a std_logic_vector input of the entity.
cos_init nd sin_init are signals of that kind: constant cos_init : sfixed (1 downto -14) :="0010011011011101";

Thanks a lot!
 

Simple answer- stop thinking like a programmer. For synthesisable vhdl you should hardly ever use a variable. Before you write any code, think about the circuit you're trying to achieve and even draw it before coding. You current code tries to complete all of this arithmatic in a single clock cycle. There is no need for this. Make everything a signal and you've got your pipeline.
 
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    Flo89

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Okay I will try this! This was just my first approach and I wanted to synthesize to see if it fit's my requirements or not.
But variable or signal, one problem is left. Is it possible to throw away the overflow bit of the addition just by doing something like this:

Code: 
sin_tempn := sfixed(std_logic_vector(15 DOWNTO 0)(sin_temp - (cos_temp srl i)));

This code is not working but perhaps there is an trick to get it working?

Thanks!!
 

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