Questions about verilog model for Analog IP

[ajianer]

Hello everyone:

Could you help me on the following questions:

1. Which information are included in the verilog model?
2. In which design flow we must use the verilog model?
3. How to deal with the analog signal in verilog model? Can anybody show me a example about ADC or DAC model?

Thanks very much.

 

[rakko]

Usually, for every input and output in your analog block, you need to measure the capacitive load and drive strength of each line and substitute a digital cell with those cell characteristics. It maybe necessary to modify the digital characteristics of the cells to make them match those of the analog ones. The analog IO characteristics are usually in the device's datasheet or you can get them from the designers of those blocks. In a nutshell, you need to model every valid analog pin and valid paths trough your analog design blocks with their digital equivalance. A very time consuming process with no easy answers. At least that I know of!

Does anyone know of an elektronic cad software to help with this process??