Questions about ULN2003

[High school electronics e]

Regarding the questions raised by the ULN2003 date sheet: First, the output current of each unit can reach 500mA, so can the full-load output reach 3.5A? Second, are there any limitations to the use of ULN2003? The safety threshold temperature is 125°C. I am using ULN2003 SOP16. What is the relationship between temperature and the power that ULN2003 can withstand?

--- Updated Dec 29, 2023 ---

This is the datasheet for reference

 

[barry]

It's all there in the data sheet. Vcesat= 1.4v. At 500ma, that's .7W. Thermal resistance is (I think) 105°C/W. That's 70 degree rise over ambient. That's per driver. You'll need some kind of heat sink.

 

[FvM]

First, the output current of each unit can reach 500mA, so can the full-load output reach 3.5A?

Datasheet figure 6.5 clearly tells no.

 

[KlausST]

Hi,

TPL7407 is a MOSFET type driver. It has less voltage drop, but also less total current.

If I was in your place, I´d use individual logic level MOSFETs. With low R_DS_ON they easily can drive 500mA each with almost zero power dissipation (heat) - compared to the ULNxxxx devices.

Klaus

 

[D.A.(Tony)Stewart]

Try to derate all thermal specs by 50% for reliable operation for ALL DESIGNS in future.
e.g. 1/8W for 1/4 W resistors .

use Ohm's Law for Thermal resistance and temp rise.

T rise = (Rjc + Rc-sink + Rsink-ambient )['/W] * Vce*I(total)[W]
above ambient which includes enclosed space.

Sometimes they show plots for max power vs Ambient (minimal power derating)
So always choose less otherwise chip will be 125'C inside or worse.
Gang ports in parallel if undersized, to share current.

 

[danadakk]

Although datasheet states outputs can be paralleled it has no supporting data
how effective that share would be, eg. will one output carry much greater
current than the other if paralleled.

One of the datasheet primary limitation is 150 C Tjmax. And as pointed out by
Stewart that needs margin.

Regards, Dana.

 

[FvM]

Although datasheet states outputs can be paralleled it has no supporting data
how effective that share would be

Yes and no. Figure 6.4. and 6.5 (simultaneous conducting) can be considered as an upper margin for current capability in parallel operation. They don't guarantee however equal current sharing.

 

[D.A.(Tony)Stewart]

Generally PN jcn. Rs bulk resistance variation is all that varies when operating as a switch. With the same die or even wafer , they are well-matched but not all wafer to wafers.

The same applies to LED Vf when in an array for parallel sharing as they are thermally coupled. If not, then divergence will/may occur with acceleration as temperature rises and the differences are more sensitive.

Darlington Vce saturation is the combination of Vbe of Q1 plus the difference between Vcb and Vbe of Q2. When saturated, this has a somewhat linear Rs resistance (bulk resistance). Thermal coupling tends to null minor variations within the chip.

Like on Class AB power amps, Rs is added to the emitter to normalize/equalize r_pi + Re where Re is chosen near r_pi for optimal low impedance when thermally coupled due to discretes not always from the same batch.

 

[danadakk]

My production knowledge very dated, in 70's we mapped variation of characterization
from middle of die out to edge, always quite a variation.

And of course in packaging die scrubin caused variation in thermal behaviour, as well as electricals.
On top of that test machine/probe card/environmental chamber, phase of the moon caused issues.

Are all those issues pretty much behind us now ?


Regards, Dana.

 

[barry]

Regardless of the linearity of bulk resistance or r_pi, or any of that, the MAIN issue here is dissipating 6 Watts. As Klaus points out, it makes way more sense to use MOSFETs than a 20+ year old part and a heat sink as big as a toaster.

 

[D.A.(Tony)Stewart]

RIP good old "hammer driver" re-branded as "Peripheral driver and Actuator"

TPIC2701 can do 3A pulse but Must not exceed 0.5A total continuous

7-CHANNEL COMMON-SOURCE POWER DMOS ARRAY

So both Darlington and DMOS arrays are thermally limited to 500 mA which is usually suitable to use only one at a time to it's 500 mA limit

 

[oscillationeer]

Regarding the questions raised by the ULN2003 date sheet: First, the output current of each unit can reach 500mA, so can the full-load output reach 3.5A? Second, are there any limitations to the use of ULN2003?

The section 6.1 of that data sheet says the absolute maximum (presumably a wire-melts limit)
for the emitter current is 2.5A; that means that the 500 mA peak currents of five inputs
will push it to the limit, and leave no margin for a sixth or seventh to turn on.

All of the output collector pins that sink current, do so through the single 'emitter' electrical terminal,
and there is no reason to expect the chip to survive an overcurrent through
that little pin #8.