Questions about SRAM Layout Rules

[BrownieHaHa]

Hi everyone, I have encountered some issues:
1. In the SRAM layout rules TSMCN28 HPCP process, there is a rule called RODMY, as seen in Figures 1 and 2. I do not quite understand this rule.

Figure 1

Figure 2​

2. In the SRAM layout from the TSMC Memory Compiler, there are rectangular Contacts (which are crucial for size reduction), you can see these 2 rectangular contacts in Figure 2. I did not find the related DRC rules for these rectangular via holes in the TSMC CLDR002 and CLCL054 documents.

3. Similarly, in the SRAM layout from the TSMC Memory Compiler, there are layers numbered 30;21 and 30;22, named CO_TESTB and CO_TESTC, respectively. Obviously, these are related to Contacts. These two special Contacts cover/partially cover the special Contact between the gate and the active region of the SRAM, as shown in Figure 3. I did not find the function and rules for these two layers in the TSMC CLDR002 and CLCL054 documents.

Figure 3​

I look forward to your guidance!

 

[npardeepsain]

These are defined layer used in TSMC provided cells. You can refer to DRM for more details.

 

[dick_freebird]

I have no specific guidance but the RAM bit cell is often given certain liberties as it's high leverage. Once the cell has been blessed the what-if and margin built into general rules decks no longer applies (though in design it "mostly did" but for a few details that make things pack better, enough to be worth the gamble. Or just the best of whichever cheating / shaving gambles survived the yield, char & qual gauntlet).

 

[BrownieHaHa]

These are defined layer used in TSMC provided cells. You can refer to DRM for more details.

Thanks for your reply. I do have the DRM for this process (though it might be incomplete). I checked the documents CLCL054 (which describes SRAM-related information) and CLDR002 (which contains most of the design rules), but I couldn't find the specific information I was looking for. If you know the exact document where I can find the relevant information, please let me know. Thank you very much.

 

[BrownieHaHa]

Thank you very much for your reply. I can understand what you're saying. Indeed, from the perspective of using SRAM, we mainly need the lib and lef files, along with some more specific timing details, and finally to merge GDS. However, the reason I am asking in such detail is because I am studying SRAM design myself. I'm also reading literature on SRAM design, but without exception, they tend to be somewhat detached from industry practice or quite general in their explanations. Therefore, I want to deepen my understanding further.

I have no specific guidance but the RAM bit cell is often given certain liberties as it's high leverage. Once the cell has been blessed the what-if and margin built into general rules decks no longer applies (though in design it "mostly did" but for a few details that make things pack better, enough to be worth the gamble. Or just the best of whichever cheating / shaving gambles survived the yield, char & qual gauntlet).