questions about (rdf0126_ddr2_mem_tutorial), spartan 6 sp601,

hello everybody..
while i convert the example (rdf0126_ddr2_mem_tutorial) of MIG in SP601 to vhdl i forced some of error:
how can i convert the sentences shown below to VHDL ???? :
// ========================================================================== //
// Error Grouping //
// ========================================================================== //
PULLDOWN zio_pulldown3 (.O(zio3));
PULLDOWN rzq_pulldown3 (.O(rzq3));

thanks in advance

- - - Updated - - -

and also can i mixed verilog and vhdl module in one project??
because i forced many of trouble in converting verilog to vhdl ,so i cogitate if there is any method make the main project in vhdl and add source as verilog ??

- - - Updated - - -

And how can i convert the sentences shown below to VHDL??

c3_p0_wr_data = {C3_P0_DATA_PORT_SIZE{1'b0}};
c3_p0_wr_mask = {C3_P0_MASK_SIZE{1'b0}};