elektor
Member level 3
First Encounter
1. After partitioning I get the design which consists of several parts, but they lack power/ground pins. How to create the pins so that I can connect supply wires inside the blocks to them and connect the wires at the top level to the pins of the block as well? Creating pin guides wouldn't help since the power nets can't be used as an input to pin guides.
2. The partitioning part of the designing doesn't seem to be so troublesome as the concatenating the design is. How to do this? I partitioned the design using FE , had the blocks placed and routed with Silicon Ensemble (and I've got all the resulting files like sdf, verilog netlist etc. for each of them) and I've got the top level which consists of black boxes of these blocks. So how to get the full design again (how to assemble the blocks): the top level with routed blocks which is needed to write out the gdsii file? Also, how to get one sdf and verilog file for the whole design?
1. After partitioning I get the design which consists of several parts, but they lack power/ground pins. How to create the pins so that I can connect supply wires inside the blocks to them and connect the wires at the top level to the pins of the block as well? Creating pin guides wouldn't help since the power nets can't be used as an input to pin guides.
2. The partitioning part of the designing doesn't seem to be so troublesome as the concatenating the design is. How to do this? I partitioned the design using FE , had the blocks placed and routed with Silicon Ensemble (and I've got all the resulting files like sdf, verilog netlist etc. for each of them) and I've got the top level which consists of black boxes of these blocks. So how to get the full design again (how to assemble the blocks): the top level with routed blocks which is needed to write out the gdsii file? Also, how to get one sdf and verilog file for the whole design?