questions about comparater offset

[xiaofeixia]

comparater

i simulated a high-speed latched comparator with preamplifier in tsmc 018 process, when i simulate the input offset i use the pch_mis and nmos_mis model(include delta(Avt,w,l,tox)) for only input and latch mosfets
but the results show a high offset:
mean = -11.1877m varian = 13.1798m
sigma = 114.8033m avgdev = 83.3351m
who can help why? thanks

 

[renwl]

because there're no offset cancel circuit, the high offset is reasonable.

 

[xiaofeixia]

you see the Vos mean value is 11mv and the sigma value is 114mv, i think if i only consider the offset of input and latch mosfet(m5,m6,m7,m8 ) , so the sigma value will not be so high

 

[raduga_in]

I feel this paper might help you a bit ..

 

[xiaofeixia]

raduga_in, really thanks, i have this paper and in fact, i use the same arichitect, the comparator is similar, too.
but the simulation show a bad result, do you know if there is something wrong with my simulation?

Added after 4 minutes:

i use the same simulation method in this paper and my comparator power dissipation is 1.5mW under 1GHz