I have used few I/O pins of Spartan 3 for realizing power sequence, the time interval between them is critical.
The problem is when power on the whole system, during initialization time all those I/O ports are driven to high at same time and then all are driven to low.
The problem is above situation is impossible to realize power sequence since all I/O ports are driven to high at same time and will turn on all Mosfet.
There are no way to control I/O until the end of the configuration process, unfortunately. You can use DONE signal to control external devices at startup.
If pin HSWAP_EN is low, all the I/O pins will have pull-up resistors (a few kilo-ohms) during configuration.
If pin HSWAP_EN is high, all the I/O pins will float (high-impedance) during configuration.
You could tie HSWAP_EN high to float the I/O pins during configuration, and then install your own weak pull-down resistors to hold the I/O pins low during configuration.
You could tie HSWAP_EN high to float the I/O pins during configuration, and then install your own weak pull-down resistors to hold the I/O pins low during configuration
Anything specified in UCF or VHDL/Verilog/schematic is unknown until after configuration. You will need to add external resistors to weakly pull the lines low or high during power-on and configuration.
If that still leaves power-on sequencing too unpredictable, add power-on counters (for delay) or a power-on state machine to your design.
If it is true I can set RC delay circuit to delay 2 second before power of 74LVT04 rearchs 2.5V ?
Ideally, if the input remains low as the power rises, the output will rise. And if the input rises as the power rises, ideally, the output will remain low. If the input is unpredictable or rises partially, the output can be unpredictable.
If I use RC circuit to enlarge the power rising time to the inverter and the input rising time to inverter follows the I/O rising timing set by FPAG without RC power delay.
What is the result?
Some guy said if use this way the inverter can be damaged.