Question Verilog HDL

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bzu

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Hello !

" using Verilog HDL "
i want to desgin 2 -bit comparator by 2 x 4 decoders and
any other gate required

" module
.
.
.
.
end module "

please its very important to me
thanks
 
Last edited:

its a project its important just for points
please any one can help me ?
 

bzu said:
please any one can help me ?
Click to expand...

Yes. You.

At least pretend to put in some work yourself. When you are stuck with something, please post your code and ask specific questions about specific problems. Plenty of people are willing to help then. But "h4lp, too lazy, plz do my work kthxbye" type of posts generally will be ignored.
 
i will try ok !
iam not lazy but i dont know
i will use my simple information
 

i will try ok !
Click to expand...
okay.

Two simple things you can do:
- google on things like "verilog comparator" or "verilog <whatever_you_have_to_design>
- read a good verilog book, or use a tutorial like this: https://www.asic-world.com/verilog/veritut.html

Should you find some example verilog code for your design, and don't understand it ... you can then browse through the above tutorial and try and read the verilog code.
 

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