habbas33
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hi
I am little confused regarding the generic usage in vhdl... I am trying to understand some reference code and I found this...
my confusion is that if data width assigned using generic (appdata_width) is 64 bit, how we can assign 128 bit data to the bus.
the code is synthesizeable and implementable and does not show any error.
I am little confused regarding the generic usage in vhdl... I am trying to understand some reference code and I found this...
Code:
generic (
APPDATA_WIDTH : integer := 64
);
port (
clk0,rst0 :in std_logic;
rd_data_out : out std_logic_vector(APPDATA_WIDTH-1 downto 0);
wr_data_in : in std_logic_vector(APPDATA_WIDTH -1 downto 0);
);
in_sel_proc : process(clk0,rst0)
begin
if (rst0 = '1') then
...
elsif(clk0= '1' and clk0'event) then
rd_data_out <=wr_data_in(127 downto 1) & '0'; -- this wr_data_in is declared 128 bit in outside module from where it is given as an input
end if;my confusion is that if data width assigned using generic (appdata_width) is 64 bit, how we can assign 128 bit data to the bus.
the code is synthesizeable and implementable and does not show any error.