Question regarding TV Tuner PLL channel synthesis

[sda]

A question regarding TV channel synthesis.
We take for instance a PLL TV Tuner using the TSA50XX series of chips.
Most, if not all, have a 4 Mhz clock.
The divisor is 512 (taken from the datasheet) which produces a 7.8125 Khz (4.000.000/512) reference.
The prescaler used (again taken from the datasheet) is 8.
Step size is : 7.8125 * 8 = 62.5KHz.

So, If we want the tuner to tune to Ch 21 for instance, the LO frequency must be :
471.250MHz (F-in)+ 38.9MHz (IF Offset) = 510.150 MHz.

To calculate N, it's 510150000/62500, which gives us 8162.4 which isn't possible.

The closest value for LO would be 510.125MHz (8162 programable divider)

This gives us a 25KHz tuning error.

Can someone confirm the above, or am I missing something?

Cheers
sda

 

[AL0117]

pll tv tuner

Hi sda,

You are right. If you need finer step, you could use 3.200 MHz crystal, in this case the step will be 50kHz, or use the TSA552x family, and playing with the ratio select bits (RSA and RSB) you can select with a 4 MHz crystal between 31.25, 50 and 62.5 kHz

rgds, Al

 

[sda]

tuner pll kontrol

Thanks for the confirmation.
I was wondering why use 4Mhz crystals in tuners, when 3.2Mhz would have been more precise. Looks like the 4Mhz crystals are abundant, so they go for them.
Anyway, as you mentioned, the TSA552X series, besides having 512 and 1024 divisor references, also has 640, giving a 50Khz step with a 4MHz crystal.

Fortunately for me, I have a couple of tuners with the above chip, so I could continue designing the front-end controller

regards
sda