Question regarding to NMOS switch circuit

DZ8205

Newbie level 4
Joined
Jul 8, 2024
Messages
7
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
32
I am running a NMOS switches control circuit by LTSpice, the way this circuit works as below: when VDD7 is off VDD9 turn for 5uS to charge C1 by voltage VDD8 which is +3.3V, then when VDD9 is off VDD7 is on for 5us to discharge C1, the C1 voltage Vout is measured.

The problem I am facing is the output voltage Vout of C1 is always around +1.0V when VDD7 is on to discharge C1. Even when I use +3.3V to control VDD9 instead of +1.3V, the voltage of C1 charge to +2.1V at beginning, but +2.1V immediately dropped down to +1.0V when VDD7 is on.

Please let me know the reason for above problem and how can I make C1 to get started to discharge with voltage higher than +1.0V.

Many thanks.

DZ


 
Last edited:

0.000000000007? Really????????????????

I can't make heads or tails of your circuit. You've got two voltage sources, but 3 labels VDD8 VDD3 VDD9. You've got some pulse definition, but I can't tell which voltage source it's connected to. You've got the substrate of the MOSFET tied to ground, but the source tied to VDD3 (maybe it's VDD8)-- I think you want the substrate connected to source.

But, as Tony alluded to, you probably aren't driving the gate voltage high enough.
 
Verify Vgs > 2* Vgs(th), which is necessary for reasonable conduction and correct pulse voltage.

Try to use prefixes like p instead of strings of 0's and 10u instead of 0.000010
I have increased the VGS ( Vth = +0.22V) of two NMOS switches from +1.3V to +3.3V, and the initial Vout can reach +1.5V instead of +1.0V.

But I still confused why the voltage Vout dropped when VDD7 turns on.

Many thanks for your answers.
 

Attachments

  • new result 2.png
    33.9 KB · Views: 67
  • new result.png
    39.5 KB · Views: 52
  • Nmosfet model.png
    28.1 KB · Views: 55

I have increased the VGS ( Vth = +0.22V) of two NMOS switches, and the initial Vout can reach +1.5V instead of +1.0V.

But I still confused why the voltage Vout dropped when VDD7 turns on.

Many thanks for your answers.

 

The way I see this is you've got 3.3V, for some inexplicable reason, on the source of M34. Then you're driving the gate with a pulse with an amplitude of 3.3V==> Vgs=0.3V.
 

The way I see this is you've got 3.3V, for some inexplicable reason, on the source of M34. Then you're driving the gate with a pulse with an amplitude of 3.3V==> Vgs=0.3V.
I want use M34 to run as a NMOS switch to charge C1 to a high voltage (VDD3= +3.3V) when VCON1 is on, then VCON1 is off and VCON2 is on to discharge C1.
 

I want use M34 to run as a NMOS switch to charge C1 to a high voltage (VDD3= +3.3V) when VCON1 is on, then VCON1 is off and VCON2 is on to discharge

Ok, here’s the deal: Your circuit is a mess.
1) Vgs is too low. I’m not sure how many times we have to tell you that. But, it doesn’t matter, because:
2) Even if it was high enough, it wouldn’t matter because of the body diode which is forward biased by VDD3.

This circuit will just not work the way you think it will.
 

Pick new FETs from the library and compare.
Many thank. I will

Many thanks, I will modify my circuit.
 

Similar threads

Cookies are required to use this site. You must accept them to continue using the site. Learn more…