Question regarding the faults in a CMOS gate

I have a question regarding the faults in a CMOS gate:

" What If in a 2 input nand CMOS I short the drain and source of one pmos transistor, what would be the behaviour of the nand gate?

Re: A CMOS question

Hi,
As such this configuration has no use,
But the behavior will be that of an NAND gate but the high voltage level at the output will be lowered by Vtn.

Thanks
Shaikh Sarfraz

Re: A CMOS question

Hi,

This is logic error. The output will always at Vcc, since you short the pmos Source and Drain.

Dar

Re: A CMOS question

Hi,
Better you see the structure of CMOS NAND gate, there is series combination of NMOS between o/p and GND.
Even if source and drain of PMOS are sorted, that means VDD is applied to o/p.
However when both i/p to NMOS are 1, VDD will be connected to GND.
So for High i/p on both gates we get low at o/p
This is the property of NAND gates.
Only thing is the High voltage level at the o/p will be reduced by Vtn.

Thanks
Shaikh Sarfraz

A CMOS question

when both inputs are high, both power rails are shorted. if any one input is low, then output is connected to logic high(VDD). what are using this configuration for?

Re: A CMOS question

I am not using this conficuration for any purpose, I am trying to charcterize the circuit for different faults.
Answer given by shaikhsarfraz is correct , I think, that when both the inputs are 1, vdd and ground is short and output is zero.
and when the transistor which is short is given a zero, high voltage at output is reduced by Vtn.

Thanks for the replies.

A CMOS question

hi,
i still dont get how the o/p is lowered by vth , the o/p is directly connected to Vdd then it is Vdd , if the NMOS are ON they are acting as resistance but the o/p willl be also Vdd and the NMOS ON resistance will have the Vdd drop.
can u clarify to me what u mean?
thnx

Re: A CMOS question

Hi,
Yeah I was wrong.
Actually for the NAND gate with this configuration for Both I/P's High, we get logic Low at the output. VDD shorted to GND.
But for other combinations 01 10 00 we get output the O/P's are either Vtn low or above the Low level.
I cann't intepret the results now.

Can anybody help?

Thanks
Shaikh Sarfraz

Re: A CMOS question

"What If in a 2 input nand CMOS I short the drain and source of one pmos transistor, what would be the behaviour of the nand gate?"

As I see it, first you'll no longer have a NAND gate. In fact, the only gate I'll see you having is a gate that, upon certain condition, takes out your 5v source.

If one of the p-channel MOSFETs is shorted from drain to source, without a doubt the NAND's output will be stuck high. However, if both inputs are high, this turns on both n-channel MOSFETs (which produces the low output of x=(ab)'); hence, that output that's stuck high will try to remain high through the two on MOSFETs, very low resistances. This will pull a lot of current from the 5v source (I=5/1=5A, as ballpark est.) Hence, assuming your 5v source remains cranking out the current, you'll likely have your gate get hot and pop like a fuse. Then your output will really be stuck high, as the low impedance shorting it out, when the inputs are high, will be gone via the destruction of one or both of the n-channel MOSFETs, due to excessive Id's.

In practice though, your supply will probably go into current limiting whenever the inputs to the defective gate are highs, for this will pull down your supply. But, it is likely that the same supply for your output is the same supply for your inputs, so look for them to go down as well, could even pulse between low and a higher low depending on your driver circuitry, as the inputs barely turn on the n-channels which short the supply, which turns off the n-channels, which raises the supply, which turns on the n-channels, and so on.

Come to think of it, have some fun and build it. Take a CMOS NAND and tie the output to Vdd. Go for the max pyrotechnics option and use a high current Vsource. Otherwise, you'll probably just get the boring oscillator or pop the circuit breaker. Be sure to rig up two switches for the NAND's inputs of course, as the fun will only begin with A=B=1.

ABX
001
011
101
110

Yeah, the one one is what you want.

What are these horns growng from my skull about? ;-)

Hmm... Can I spare a CMOS NAND gate?...

Added after 5 minutes:

I just gotta do this.

All I need is a battery, a bread board, jumper wires, and a CMOS NAND.

I'll let you know what happens.

Added after 29 minutes:

Sorry, can't spare a NAND...

But I can spare a NOR, which is an inverted NAND. (The two p-channels to Vdd are now n-channels to Vss, and the two n-channels to inputs are now p-channels to inputs. The NAND circuit's been inverted.)

Where the NAND was to be shorted high, blowing its cookies via a one one, the NOR will be shorted low and blow via a zero zero combinaton.

Other than that, it's the same thing.

I predict, as I'll be using a battery, my battery gets hot with the zero zero combination only and that the gate pops if I leave its output shorted to ground long enough, which will leave the output low, through hard shorted n-channels and blown open p-channel(s).

Deliberate destruction of defenseless parts, will I have to see a priest after this?

Added after 36 minutes:

Well, I must have left something out of the mix somewhere.

Given a 6v, 5 or so amp supply, a defenseless 4001, with a=b=0 and x=0, I got a wopping 8mA draw and a 4001 that's no worse for wear (although I won't use it again for anything real.)

So where did I get 6v/8mA=750Ω of limiting resistance?

I tested the NOR both before and after the experiment and it worked. I didn't know that CMOS gates have current limiting. That's nice to know, especially with me at the wheel. But where did that R come from?

Added after 16 minutes:

No answers yet but I have found that the NOR internal circuit is actually a NAND with inverted inputs and outputs. But still that CMOS inverter at the output had an on p-channel shorted to Vss??

Is the on p-channel's Rds_on=750Ω??

Re: A CMOS question

Hi,
As you have said that in the NAND gates, the Source and Drain of the PMOS is shorted means there is no use of the PMOS as VDD is directly connected to output.
Now it is simply an NMOS logic, and because of the NMOS connected in Series it will behave as an NAND gate.

Thanks
Shaikh Sarfraz

A CMOS question

dear Shaikh,
the o/p is connected to Vdd directly which means that it is fixed to Vdd unless something like direct connection to ground or other supply happens which is not the case here, so i THINK that the o/p is a fixed high logic.
note: u seem to consider the NMOS that are ON as SHorts and hence consider o/p connected"shorted" to GND which is not true as the ON MOS has ON resistance , so u can model this as a supply connected to GND through resistance and we taking the voltage at supply which still gives high logic"Vdd"
regards,
a.safwat

Re: A CMOS question

Hi,
As the output is connected to ground when both the NMOS transistors are on the current will flow into ground.
Even if some load is connectecd to the output, what do you think will the supply VDD drive the next stage or the current will flow to ground.
ANS: The will go to ground, and the output to the next stage will be zero.

Thanks
Shaikh Sarfraz

A CMOS question

hi,
i still dont get what u r saying , if we consider the o/p is connected to a load ZLoad and in the same time connected to the Ron , then Zload and Ron are parrallel and they have the same voltage drop Vdd , and the current passing through the load will be I=Vdd/Zload while the curent passing through the Ron is I=Vdd/Ron but this has nothing to do with the Voltage at the o/p which is fixed to Vdd by the supply

Re: A CMOS question

Hi,
The on resistance of the NMOS is very small, its almost like a short.
So where is the question of two resistors in parallel.

Thanks
Shaikh Sarfraz

A CMOS question

u canot consider it short if it is ideal short then the current will be infinite and the BOOM the MOS is damaged and then the o/p will be still logic high, if u neglect the large currnent effect then it is a small resistance parralel with the o/p load impedence.,
simply u cannot consider the o/p node of a supply voltage anything except its Voltage , or it will be supply no more u can consider it load that way "battery charging "

Added after 1 minutes:

btw if it is small resistance say one mOhm and the MOS can handle the high current then the o/p is as i said "dont approx. the 1mOhm into 0 Ohm", also u seem to be considering the supply as a current source while it is a voltage source
regards

Re: A CMOS question

This is logic error. The output will always at Vcc, since you short the pmos Source and Drain

Re: A CMOS question

All,

Via an experiment that started in this thread and then moved into another thread, I determined that the Ron of the MOSFET in the CMOS output is roughly 750Ω, far from a short. Granted, I experimented with a NOR and grounded output, instead of a NAND, the subject of this thread, but the results would be the same. Ron is approximately 750Ω, and, as such, my source current was limited to around 8mA.

(I'd also assumed Ron was close to zero, but found I was wrong. Likewise, the source and sink current graphs in the datasheet reflect this high Ron, where someone even posted one of those graphs in the other thread.)