santhosh.vlsi
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Hello all,
Please provide me the details about memory compiler(generator).As per my knowledge compiler generates the cut according to user specifications.What parameters we have to consider in cut generation, like how to consider MUX,WORD,BIT parameters.apart from these three parameters any thing else to consider and how my top level memory look like after generation of layout.
1. Which specific tool used in cadence as memory compiler.
2. Insight on Memory leaf cell
3. what is the role of memory layout/design engineer in the VLSI industry.
Thank you
Please provide me the details about memory compiler(generator).As per my knowledge compiler generates the cut according to user specifications.What parameters we have to consider in cut generation, like how to consider MUX,WORD,BIT parameters.apart from these three parameters any thing else to consider and how my top level memory look like after generation of layout.
1. Which specific tool used in cadence as memory compiler.
2. Insight on Memory leaf cell
3. what is the role of memory layout/design engineer in the VLSI industry.
Thank you