Would you mind to draw a transistor level circuit and explain where you see two signal inversions respectively 360° phase shift? Obviously there's only one signal inversion, switching the loop phase by 180 degree. The oscillation condition could be fullfilled if the loop gain has three poles providing additional 180 degree phase shift
3) The feedback loop automatically presents a 180 phase shift of the signal
Here is a schematic: View attachment 121826
The NMOS inverts the signal by 180. A feedback path is by default a 180 phase shifter. Doesn't this sum up to the 360 phase shift?
...by default? Where do you see a path with additional 180deg phase shift?
...by default? Where do you see a path with additional 180deg phase shift?
Yes - 180deg because negative feedback is established by the common source configuration.
However, where do you see ADDITIONAL 180 deg phase shift?
For an additional 180 phase shift if I use another inverter to create a two inverter oscialltor, the system will latch. So the solution will be to use three inverter stages.
But then again, the total phase shift will be 180*3?
Yes, 180*3 - however, at DC only!
But for higher frequencies there is a time delay (intentional or unintentional) that is connected with additional phase shift. This allows oscillation at a frequency which results in 360 deg phase shift.
Hi LvW, can you kindly explain that sentence again? Are you saying at any frequency apart from 0, only two inverters are working and hence produce a 180*2 =360 phase shift?
Now - the total delay (total phase shift) must be selected/designed with the aim to produce additional 180deg at the desired oscillation frequency fo. (Another 180 deg are caused by the odd number of inverters).
A single inverter stage produces 180deg phase shift - in idealized THEORY only!
Didn`t you hear about parasitic capacitances (causing delay and additional phase shift for large frequencies) ? What about the input capacitance of the next stage?
What happens when you have an additional grounded capacitor at the output of each strage? This capacitor - together with the output resistance of each stage - forms an RC lowpass.
And a lowpass causes phase shift.
You must keep in mind that there is no IDEAL transistor inverter.
So ultimately, is the phase shift caused by the inverter or the RC of each stage? Or both?
Cause the inverter causes a 180 phase shift and a RC causes a 90 phase shift.
No - an RC lowpass causes a phase shift starting at 0 deg (DC) and assuming -90deg at infinite frequencies.
Therefore, a chain of 3 inverters can have a phase shift of (-3*180 - 3*60)=-720 deg (identical to 0 deg).
However, this applies to one single frequency only, which produces an additional phase shift of -60deg for each inverter stage.
Again: NO!
If you carefully read again my answers 6, 8, 10 and 12 I am sure you will find the answer by yourself.
Here is my understanding so far. Correct me if I'm wrong
1. A CS stage produces a 180 Phase shift at DC.
YES, but it is logical to consider it as -180deg
Any frequency above DC/ parasitic caps cause the phase shift to reduce.
No - delays and RC stages cause additiinal negative phase shifts.
So at an infinite frequency, is the phase shift of a CS stage 0 degrees? (Because the input just passes to the output through Cgd)
No - it makes no sense to consider infinite frequencies (because the do not exist). It is only a theoretical consideration to say that an RC element shift s the phase by -90 deg at infinite frequencies.
2. A RC produces 0 phase shift at 0 frequency and 90 phase shift at infinite frequencies.
Yes
Now, is a 3 stage ring oscillator modelled as 3 inverters alone or 3 inverters along with 3 RCs?
As you like: When the signal delay alone is used to cause the necessary phase shift for oscillation the frequency will be very high and not known exactly. If you use additional RC stages you can determine the frequency at lower values
Assuming it is modelled as both, at fo, a signal sees 6 components that want to shift its phase? Is this right?
Yes
As all C's are actually inside the transistors, there's no additional RC. In your circuit, you have additional load R in parallel to the transistor output impedance, but not additional C.Now, is a 3 stage ring oscillator modelled as 3 inverters alone or 3 inverters along with 3 RCs?
As all C's are actually inside the transistors, there's no additional RC. In your circuit, you have additional load R in parallel to the transistor output impedance, but not additional C.
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