Question regarding Chip PLLs and Passive Filters

[AdvaRes]

nwell cap

Hi all,
I have a question regarding on Chip PLL. Is it better to implement the filter on chip with the PLL or construct it by using off chip capaciatnces and resistances ?

In fact I realized that the on chip filters capacitances have a big area.

 

[saro_k_82]

npoly nwell cap

It depends on how big the loop filter components are.., It is preferable to keep it on-chip to reduce the parasitic inductances of the path. Also it avoids a pin on the package, but it is preferable to have access to the VCTRL node during testing.

 

[ravirajdv]

Re: PLLs and Passive Filters

Hi,
If the capacitor is of the order of uF's then naturally having it off-chip make sense, but having the components on-chip is good as we can avoid a lot of parasitic paths, extra pin for the chip, ESD's and noise (due to pin), can have programmability added for the the loop components by controlling few bits.
off-chip advantages if any??
Regards,
RDV

 

[saro_k_82]

Re: PLLs and Passive Filters

The component parameters are small enough to be placed on-chip. You can try moscaps to reduce the area considerably, if the leakage is negligible.
What is the setup for the phase noise sim?, is it for the whole loop? is this after extraction? What is the carrier's amplitude?

 

[ravirajdv]

Re: PLLs and Passive Filters

Hi AdvaRes,
I guess its a poly resistor and a npoly-nwell cap that is being used. I think it would be better to use a nwell resistor, advantage being a less no. of resistor heads (contributing to noise) and also less resistor area.
I feel there are 2 disadvantages of a moscap
1> low cap density compared to the poly-nwell cap.
2> the mos device has to be in saturation otherwise we can see a lot of effect on the cap (if the mos sees a transition between different regions for reasons unknown).

Thanks,
RDV

 

[sandeep_torgal]

Re: PLLs and Passive Filters

I feel there are 2 disadvantages of a moscap
1> low cap density compared to the poly-nwell cap.
2> the mos device has to be in saturation otherwise we can see a lot of effect on the cap (if the mos sees a transition between different regions for reasons unknown).

I didnt get the second point. For a moscap, the device will not be in saturation since the Vds=0.
The accumalation, depletion, weak inversion, or inversion depends on the charge applied to the gate wrt substrate. Let me know if there are other views.

Regards,
Sandeep

 

[saro_k_82]

Re: PLLs and Passive Filters

1. As far as I know MOS caps are the best when it comes to cap density., they have nothing else in their favour (high series resistance, bottom plate cap, leakage current, non-linearity wrt to voltage etc)
2. what ravirajdv probably meant is that the MOSFETs must be biased in strong inversion. This wont be a problem in PLLs because the CP can't work all the way to the supply and this 200mV or so is normally good enough to bias the moscaps to the region where they are fairly linear.

 

[ravirajdv]

Re: PLLs and Passive Filters

Hi Saro_K_82,
If we take a mos device say nmos we have gate as one terminal while the other terminal is a source and drain n-diff in a p-substrate. The channel has to invert (invert strongly) and form another plate along with source and drain diffs.
In contrast if we have a cap between poly and a nwell, I think the cap density should increase. Also we should be able to characterize the ESR of the device precisely. This should also improve on the linearity of the device.
Truely the mos is going to have less leakage since there's no big chunk of nwell beneath it.

Thanks,
RDV

 

[saro_k_82]

Re: PLLs and Passive Filters

The thinnest dimension in the chip is the oxide thickness.., coupled with high eox, there is nothing to beat the cap the moscap provides when it comes to density.

Talking about the ESR, it arises only because of the poly which is common to both types, with higher density for MOS caps coupled with low channel resistance(compared to well resistance), they will exhibit higher Q than poly-nwell types.

The thinnox is the most tightly controlled parameter in the CMOS process and so the variation in the MOS cap value is found to be the least.

The CP output comes from a drain of a MOS transistor in saturation and the LPF output goes to a gate of a MOS transistor in saturation(or a varactor which again is a MOS). So there is no case where the MOS cap is in need of bias. The variation in the cap value for MOS caps from 200mV to 1.2V is very less in 90nm and below process.

Finally poly-nwell caps also have voltage dependence.

 

[ravirajdv]

Re: PLLs and Passive Filters

Hi AdvaRes,
You will have to put the substrate rings or guard rings around the cap and the resistor. Usually the process specifies that we need to have substrates contacts say for every 30um. A quick run of the Design-rule check should give you these errors.
Usually when you run LVS the tool tries to find the substrate contact within some area so that it can relate/identify the substrate to a particular device. In the present scenario I think you might not have put any substrate contacts near these devices.
Check these.

Regards,
RDV