Question on Writing timing constraints for a given scenario

A Basic Query on timing constraints.

Assume I have a block with an input port (in1) feeding the D pin of a flop and the Q pin of the same flop is connected to a combo logic and this combo logic feeds another flop , the output of this flop feeds an outport port (out1).Both flops are fed by the same clock.

You are asked to constrain this block given the following conditions: Input and output should be constrained at 60% of clock period. The combo logic between the two flops has to be constrained at 20% of clock period.

Here is what I think should be done

1) set input delay at 60% of clock period
2) set output delay at 60% of clock period
3) set max delay between Q pin of flop1 to D pin of flop 2

Have I missed something here.Please help. I feel something is missing here.

Basically it is a set up time problem.
Clock_period > clock_to_q(first_flop) + logic_delay + setup_time_of_second_flop

http://www.vlsi-expert.com/2011/05/example-of-setup-and-hold-time-static.html#.UVTb4hiVv0M

This link explains clearly as to what setup and hold analysis will give you the max frequency. You can put the %age above to the get the solution.

artmalik said:

Basically it is a set up time problem.
Clock_period > clock_to_q(first_flop) + logic_delay + setup_time_of_second_flop

http://www.vlsi-expert.com/2011/05/example-of-setup-and-hold-time-static.html#.UVTb4hiVv0M

This link explains clearly as to what setup and hold analysis will give you the max frequency. You can put the %age above to the get the solution.

Click to expand...

Hi,

I am not looking for the method to calculate the max frequency of this circuit.Nor am I looking for the setup or hold check equation.

What I am looking for is given the above circuit, write timing constraints in Prime Time to correctly constrain the circuit.Assume a clock period of 1 ns.

Can anyone help me on this.