Question on variation of Intrinsic gain with Vds

Status
Not open for further replies.
M

micro designer

Junior Member level 2
Junior Member level 2
Joined
Mar 23, 2011
Messages
23
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,283
Activity points
1,432
Hi

I am following the EECS 240 Analog IC Circuits Course Online. In Lecture 4 a testbench is given to simulate the gain avo of the mos while sweeping Vds. In the plots the gain is as shown in this fig View attachment gain vs vds.pdf

My doubt is why the gain is decreasing when Vds is approaching VDD (1.8V). I have repeated the same thing in Cadence using 180nm UMC process but in that gain stays at the maximum value it doesnt decrease after certain Vds.

Thanks
 

The gain reduction (at larger Vds values) shown in your PDF is due to charge carrier velocity saturation (mobility reduction due to the longitudinal field) and/or due to vertical field mobility reduction (VFMR), which is more distinct in short channels (longitudinal field strength) and in thin oxide transistors (vertical field strength).

Perhaps you used either a longer channel or a higher voltage transistor (thicker oxide) for your comparison test?
Also, a lower Vth value ( -> lower Vgs) reduces the VFMR effect.
 
Can you also compare the threshold voltages (named VT in slide 10 of EECS240 Lecture 4) and the oxide thicknesses (tox) of both processes?

Perhaps one of these (or both) differences are responsible for the different gain behaviour (due to VFMR effect).
 

micro designer said:
I am following the EECS 240 Analog IC Circuits Course Online. In Lecture 4 a testbench is given to simulate the gain avo of the mos while sweeping Vds. In the plots the gain is as shown in this fig View attachment 92339
Click to expand...

BTW: Did you use the same testbench? Did you notice, then, that in slide #10 the opAmp's inputs are interchanged? vds should be connected to the non-inverting input, the feedback from the drain to the inverting input.
 

In real life I observe that the classical saturated drain
characteristic is an academic fantasy, and there's a lot
of "curl" to the ID-VD curve. Making Rout reduce, and
there goes your gain. SOI kink effects are even worse.
Even in a well behaved technology that hasn't been
"optimized" to the bone, leakage vs reliability vs speed,
higher Vds shortens your channel and will lower Rout,
while you are also perhaps forced away from peak gm
current densities (for that drain operating point - peak
gm position varies).
 

Status
Not open for further replies.

Similar threads