Question on resetting CCO Verilog-a model

[livecf]

Hello,

I want to build a CCO model that can take external reset signal and using idtmod() function to integrate.

The code I got looks like this:

analog begin

ip = -(I(IBOT_P));

if ((V(RESET)-vth>0)) begin
freq_p = 0;
end
else begin
freq_p = KICO*(ip)+ Fc;
end

phase_p = idtmod(2*`M_PI*freq_p,0,`M_PI,0,1p);

$bound_step(1.0/(step*Fc));

V(PH_P) <+phase_p ;

end

The problem is when reset is active it just hold current value, and later starts again from that previous position. I want the integrator to start from 0 again after reset is low.

Any comment is appreciated.

Thanks