question on power analysis, after synthesize the verilog RTL model

[jj00510]

Is it possible that the reult of power analysis of disign improved after adding more function in verilog code?

 

[ThisIsNotSam]

conceptually, you expect that more logic will consume more power. but more lines of code do not necessarily mean more logic. it might just be different logic, that maybe is optimized differently because of the changes you did.

 

[jj00510]

conceptually, you expect that more logic will consume more power. but more lines of code do not necessarily mean more logic. it might just be different logic, that maybe is optimized differently because of the changes you did.

Thank you for your response. So, even if the result differs from expectations, can I consider it a reliable outcome as long as it satisfies the timing condition? I have no idea whether the result came from my misconfigured constraints or if it's just an optimized outcome.

Thank you

 

[ThisIsNotSam]

In general, yes, you can trust the tools are giving you correct results given the conditions you set. Accuracy, however, at this level, is low. Numbers coming from physical synthesis are much more reliable than those from logic synthesis.