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Question on LVPECL Interface

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suria3

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Hi,

Do anyone can suggest me a architecture to design a LVPECL driver? Is there any standard circuit for LVPECL like we have in CML design. I know the standard for LVPECL is to have a common mode of 2.0V and the signal swing of 900mV - 1000mVpp single ended. Pls guide me on this.

Thanks,
Suria3
 

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