question on gain error of a charge scaling dac

[wholx]

gain error of dac

i am simulating a MSB voltage scaling and LSB charge scaling dac with spice. the output has a gain error of 5% and offset error of 0. i wonder how come the gain error.

according to the simulation, the MSB voltage-scaling subDAC worked very well, so the problem is within the LSB subdDAD. the influences of parasitic capacitance and on-resistance are ruled out already. the simulation showed that the initialisation before each conversion has been done as expected. anyone know any other reasons that will produce gain error?

 

[demodb]

charge scalling dac

have you considered quantization noise?

 

[sunking]

charge scaling dac

how you define the gain error?

 

[wholx]

the gain error was around 3%.

i made another test by increasing the Cmin of the charge-scaling subDAC from 1pF to 1nF. the result was good and the gain error decreased to 0.01%. so i guess this means there is a parasitic capacitance in parrallel with the capacitances in the subDAC, am I right? but the question is how come? as i said the output buffer was realised by an ideal amplifier (en element called E from the library), which i guess has no parasitic capacitance.


anyone has any idea?