Question on DFT - scan insertion

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Hello,

When we say DFT – it all comes when I use synthesis (it is understood that I have to decide dft architecture, scan compression, scan chain no), and give it to synthesis scripts and dft compiler will insert scan in netlist.

But if I take a look at rtl level – Not IP level, what should I consider?

Please correct me and share your inputs where ever I am incorrect. Appreciating.. Thanks.
 

When writing RTL, you need to consider what style of code will result in high test coverage. For example, an internal async reset make reduce coverage, unless you bypass it during scan mode. Likewise, if you are adding clock gating by hand in to the RTL, you will want to make sure the RTL enables the clock gater during scan shift. Avoid coding on-chip tri-state buses. Etc, etc. Look for some coding guidelines or in a lint rule deck for a more extensive list.
 

Adding what I think
1. Coding style is very important as mentioned in the above response.
2. checking for Pre-DFT DRC's using tools like spyglass will not only tell you the DRC's but also estimates the test coverage (~2-5% in proximity).
3. Unintentional BUS structures will cause ATPG to stop. so make sure they are not existing in RTL.
 

Adding what I think
1. design a method to enter DFT mode
2. If there are some analog circuit, make sure all the signal send to analog are suitable when chip is in dft mode
 

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