Question on CMOS hysterisis comparator design

Hi,

I'm designing a conventional CMOS hysterisis comparator.
I noticed that the hysterisis level is changing according to the input frequency to trigger the output.
For example, at 50kHz sin wave input, the hysterisis level to trigger the output is 10mV, whereby
for 500kHz sin wave input, the hysterisis level to trigger the output shows about 50mV.
Question, is it the hysterisis threshold level to change according to the incoming input signal frequency
or the threshold level SHOULDN'T be changed. I have read on some notes, the hysterisis amount is to
be controlled by varying the ratio of the feedback resistor, but in my case my, the cmos comparator design
is not using the resistor base design architecture.

Thanks
Suria

Hi,

For example, at 50kHz sin wave input, the hysterisis level to trigger the output is 10mV, whereby
for 500kHz sin wave input, the hysterisis level to trigger the output shows about 50mV.

Click to expand...

Where do you have the values from?
Is this specified in a document, or did you measure it (real hardware or simulation) by yourself.

If measured: Did you consider the input_to_output delay of your comparator?

Klaus

Hi, it is the simulated values.
Yes, from the simulation, the delay between the input signal and the output trigger signal is varying according to the incoming signal frequency.
This is understood that I should observe difference range of output delay based on the input signal frequency.
I believe the amount of hysterisis threshold level are varying according to the input freq range based on total total amount of delay incurred .

Hi,

the delay between the input signal and the output trigger signal is varying according to the incoming signal frequency

Click to expand...

I don´t think so.
There may be a little dependency about rise time of the input signal..

I believe the amount of hysterisis threshold level are varying according to the input freq

Click to expand...

I doubt this. I think you just misinterpret the results of the simulation.

Show the waveforms of your simulation.

Additionally I recommend to do a simulation with square wave input. With relatively low (not to overdrive the input stage) input signal levels, but fast edges. This should give you the delay times.

Klaus

There are two components, DC hysteresis and the
low-overdrive propagation delay.

You need to settle your test condition and specs.
You will not generally find more than a single test
condition in commercial products - never a "DC-to-
light" hysteresis band. Usually, just DC spec, which
you approach by a "slow enough" ramp (L->H and
H->L, take difference) or if using a precision input
test loop, creeping the offset level until all-low
and all-high output (no chatter) input levels are
found.

Anyway, understand your spec (values and conditions)
and work to it, don't get off in the weeds over stuff
nobody cares about.

suria3 said:

Question, is it the hysterisis threshold level to change according to the incoming input signal frequency

Click to expand...

Is it possible you have a low or high pass filter somewhere? It might be created inadvertently by an arrangement of components (a) at the input stage, or (b) in your feedback network.
Such filtering action could alter amplitude of your input signal, to different levels depending on its frequency.

KlausST said:

Hi,


I don´t think so.
There may be a little dependency about rise time of the input signal..


I doubt this. I think you just misinterpret the results of the simulation.

Show the waveforms of your simulation.

Additionally I recommend to do a simulation with square wave input. With relatively low (not to overdrive the input stage) input signal levels, but fast edges. This should give you the delay times.

Klaus

Click to expand...

Hi Klaus, back to your question. You suggested to do a simulation with square wave input. Like I ramp up and down the input from 0 to "some DC value" with 0.1us time. Let say with this ramp, I gets the output delay time of "X" second, does that mean when I apply the actual sin waves with different range of input frequency signal, my output comparator trigger time will be still in the range that I do the input ramp?

Hi,

disussion without the requested waveforms is difficult and may lead to misunderstandings....

Klaus

Hi Klaus,
Please refer the attachment.
The *_input file is the hysterisis amount I got when I apply in the triangle waveform with 100us ramp.
Whereby the file name with *_50kHz and *_200kHz is the comparator output with different set of hysteresis
with the input sinusoidal waveform of 50kHz and 200kHz.

Thanks
suria

Hi,

I have to repeat:

From post#4:

Additionally I recommend to do a simulation with square wave input. With relatively low (not to overdrive the input stage) input signal levels, but fast edges. This should give you the delay times.

Click to expand...

i recommend two input square waves with voltage levels 2.4V / 2.6V, 180° phase shifted.

Explanation: Withe the given waveforms it is hard to say what´s caused by "offset", what´s caused by hysteresis and what is caused by "delay".

*********
Your charts:
It´s more difficult to read timings and voltages from a "two signal input" picture. --> Please show one line "Vip - Vin"
It´s more difficult to compare timings when each picture has different time scale. --> Please show same time scale (and voltage scale) on all charts. Focus on the transitions.
Then maybe you need two pictures (for independent rising and falling edge)

Klaus

Hysteresis would be better displayed by changing the X
axis to be the input voltage (difference) value rather than
time.

If you like graphical methods, try plotting hysteresis span
(V) vs input slew rate divided by low-overdrive propagation
delay. If it looks like a linear relation, then there's your pony.

Hi Klaus,

I'm attaching the waveform of the square input with 0.5us rise/fall and with another one with 1us rise/fall.
As it shows in the waveform on the zoomed version, the amount of delay from input to output trigger and the total hysterisis level is varying according to
the input rise/fall signal, which I think this is the similar case to the input sinusoidal waveform with relevant frequencies.
From the simulation, it is observed, with faster rise/fall input , the hysterisis level is high than then the slower rise/fall time, whereby the input to output
delay is fast for fast rise/fall and vise versa.

So, in this case, can I say the amount of hysterisis and delay will be dependent on the incoming input frequency signal?

Hi,

Much better, but not perfect.

I asked for a square wave with fast edges. But 0.5us rise/fall is really slow compared to the output edges.

I wonder why your output is inversed. Is the shown input signal: (V_inp - V_inn)?
*****

Now let's refer to the pictures of post#12 we have...
But let's assume there are fast edges.

Then do it like in your 4th picture: you will see sharp input edges.
1) now zoom in for the rising output edge and measure the time difference to the input edge. It will be in the range of 100ns. Thus - if you want 1% precision - you should be able (zoom) to detect a deviation of 1ns. --> note down this "rising_edge_delay".
2) do the same, but with output falling edge. --> note down this "falling_edge_delay".
3) now use fast sine input (choose the frequency you like). Focus on rising output edge. Take a vertical ruler and place it "rising_edge_delay" (about 100ns) before the output edge. Use the ruler function to measure input voltage. --> note down "rising_edge_voltage"
4) same frequency but falling output edge: --> note down "falling_edge_voltage"
5) calculate: the value: (rising_edge_voltage - falling_edge_voltage). --> note this value down as "hysteresis_voltage"

Now repeat steps 3, 4, 5 with modified input frequencies (or other voltages or other waveforms as you like).
Compare the results.

Surely you may find some deviation. I wonder how big they are.

(Maybe in 2 hours I can post some pictures for explanation)

Klaus

Hi Klaus,

My apologies, I have mistakenly plotted the V_inn - Vinp, that's why the output is inverted. Could you please post me some pics of explanation as you mentioned when you are available.
I will proceed with the steps you suggested.

Hi

here the pictures:
determine the delay time:
Because of high dv/dt the measured delay time is about independent from true input_voltage_threshold level.


*****

determine true switching voltage:
1) from the above picture we know that it takes xxx time from input to output. Thus we take the output edge and step xxx back in time. This is the time where the input is expected to cross the threshold level.
2) now we measure the voltage at this point of time.


Klaus

The relation is more about slew rate about the threshold
point, than input "frequency". A square wave is mostly
boring and does nothing, until the edge shows up. And
its behavior is unlike the sine wave despite being at the
same frequency.

Delay in comparators depends on "overdrive" (zero
overdrive gives infinite delay in simulation, chatter in
real world). You can't just take "the" delay and subtract
as an index for true voltage, because the delay depends
on that same voltage's trajectory.

Here's an interesting CMOS hysteresis circuit I just made operating at 10MHz with 74HCxx inverter and Schmitt trigger.
Using a 1M Pot and 1K input R I chose the max gain of a buffered inverter to tap a ratio of the null input and output to get variable amplitude or gain to drive an ideal CMOS Schmitt trigger with thresholds at 1/3 and 2/3 Vss.

Using both an FM sweep and AM sweep you can see how I change the threshold of hysteresis by changing the gain using the excellent saturation and linear gain properties of CMOS logic as linear circuits.

Although I recall I only tried this over 40 yrs ago using CD4000 series chips.

http://tinyurl.com/y9h9sa95


You can drag the edge of the scope window higher to enlarge the view and >EDIT> Center Circuit (View of schematic )