ragramya
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hi friends,
I have started working on cadence soc encounter. when I am writing code on verilog , no errors will be found when I am doing my synthesis. But when Iam writing a code in VHDL, lot of errors are found when iam doing my RTL synthesis. Is it cadence soc encounter will only work for VERILOG, or VHDL or both.
Ramya
I have started working on cadence soc encounter. when I am writing code on verilog , no errors will be found when I am doing my synthesis. But when Iam writing a code in VHDL, lot of errors are found when iam doing my RTL synthesis. Is it cadence soc encounter will only work for VERILOG, or VHDL or both.
Ramya