Question on Arrays in Verilog

[easytarget]

Hi,

I'm learning Verilog on my own right now and I'm stuck, please help. I'm confused how arrays are referenced. Here's the code that confuses me:

//first, the declarations, I have no problem with them:

input [width-1:0] data_in;
input clk, reset;
output [width-1:0] data_out;

reg [width-1:0] pipe [0:length-1];
wire [width-1:0] d_in [0:length-1];

//now here's what's confusing me:

assign d_in[0]=data_in;
assign data_out=pipe[width-1];

My question is how can you assign values to things with different dimensions? can someone tell me which elements are assigned wich values in the above code? This is from a book called A Starter's Guide to Verilog 2001, page 136. Thanks for your help.

 

[echo47]

reg [width-1:0] pipe [0:length-1];
pipe is a group of "length" registers. Each register has "width" bits. It's a (length x width) memory.

wire [width-1:0] d_in [0:length-1];
d_in is a group of "length" data busses. Each bus has "width" bits.

assign d_in[0]=data_in;
That copies data_in to the first data bus.

assign data_out=pipe[width-1];
Oops! That looks like a mistake. It tries to use width-1 as an address into pipe.

 

[khorram]

You have specified two kinds of array, one-dimentional and two-dimentional.
The code "input [width-1:0] data_in;" specifies a one-dimentional array. It means data_in[width-1] til data_in[0] which indicates a signal by width bits.
The code "wire [width-1:0] d_in [0:length-1];" describes a two-dimentional array. This array includes "length" members that each of them indicates a signal by "width" bits.

assign d_in[0]=data_in; ----> data_in[width-1:0] is assigned to d_in[width-1:0][0]

assign data_out=pipe[width-1]; ----> pipe[width-1:0][width-1] is assigned to data_out[width-1:0]. It means (width-1)th element of pipe is assigned to data_out. In this case, "width" should be less than or equal "length".

rgds,
KH